vcs 使用--基本

1.Synopsys Verilog Compiler Simulator is a tool  from Synopsys specifically designed to simulate and debug designs. This tutorial basically describes how to use VCS, simulate a
verilog description of a design and learn  to debug the design. VCS also uses VirSim, which is a graphical user interface to VCS used for debugging and viewing the waveforms.

 

2.There are three main steps in debugging the design, which are as follows
 
1.  Compiling the Verilog/VHDL source code.
2.  Running the Simulation.
3.  Viewing and debugging the generated waveforms.

 

3.You can interactively do the above steps using the VCS tool. VCS first compiles the
verilog source code into object files, which are nothing but C source files. VCS can
compile the source code into the object files without generating assembly language files.
VCS then invokes a C compiler to create an executable file. We use this executable file to
simulate the design. You can use the command line to execute the binary file which
creates the waveform file, or you can use VirSim. 

 

Compiling and Simulating

1.  In the “vcs” directory,  compile the verilog source code by typing the following at the
machine prompt.  
 

[hkommuru@hafez vcs]$ vcs –f main_counter.f +v2k  
 
Please note that the –f option means the file specified (main_counter.f ) contains a list of 
command line options for vcs. In this case, the command line options are just a list of the 
verilog file names. Also note  that the testbench is listed first. The below command also 
will have same effect . 
 
 [hkommuru@hafez vcs]$ vcs –f  counter_tb.v counter.v  +v2k  

The +v2k option is used if you are using Verilog IEE 1364-2000 syntax; otherwise there 
is no need for the option. Please look at Figure 1 for output of compile command. 

By default the output of compilation would be a executable binary  file is named simv.
You can specify a different name with the -o compile-time option. VCS compiles the
source code on a module by module basis. You can incrementally compile your design
with VCS, since VCS compiles only the modules which have changed since the last
compilation.  

 2.  Now, execute the simv command line with no arguments. You should see the output
from both vcs and simulation and should produce a waveform file called counter.dump in
your working directory.

[hkommuru@hafez vcs]$simv 

 

VIRSIM TUTORIAL

3. We can now re-invoke vcs to view the waveform. At the unix prompt, type:

[hkommuru@hafez vcs]$ vcs –RPP counter.v