Circuits ---Sequential---Latches

1. D flip-flop

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//
 
    always @(posedge clk)
        begin
           q<=d; 
        end
 
endmodule

2.D flip-flops

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    
    always@(posedge clk)
        begin
           q<=d; 
        end
 
endmodule

3.DFF  with reset

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
 
    always@(posedge clk )
        begin 
            if(!reset)
                q<=d;
            else
                q<=0;
        end
    
endmodule

4.DFF with reset  value

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
 
    always@(negedge clk)
        begin
            if(!reset)
                q<=d;
            else
                q<=8'h34;
        end
    
endmodule

5.DFF with asynch reset

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
 
    always@(posedge clk or posedge areset)
        begin
            if(areset) // 高电平有效
                q<=0;
            else 
                q<=d;
        end
    
endmodule

6.DFF with byte enable

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    
    always@(posedge clk)
        begin
            if(!resetn)
                q<=0;
            else
                begin
                    if(byteena[1])
                        q[15:8]<=d[15:8]; //修改
                    else
                        q[15:8]<=q[15:8]; //保持
                    if(byteena[0])
                        q[7:0]<=d[7:0];   //修改
                    else
                        q[7:0]<=q[7:0];   //保持
                end
        end

endmodule

7.D Latch

module top_module (
    input d, 
    input ena,
    output q);
    
    always@(*)
        begin
            if(ena)
                q=d;  //仍然是顺序元素，采用非阻塞
        end

endmodule

8. DFF_1

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);

    always@(posedge clk or posedge ar)
        begin
            if(ar)
                q<=0;
            else
                q<=d;
        end
    
endmodule

9.DFF_2

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
    
    always@(posedge clk)
        begin
            if(!r)
                q<=d;
            else
                q<=0;
        end

endmodule

10.DFF gate

module top_module (
    input clk,
    input in, 
    output out);
    
    always@(posedge clk)
        begin
           out<=out^in;   
        end

endmodule

11.Mux and DFF_1

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
 
    always@(posedge clk)
        begin      
            case(L)
                1'b0: Q<=q_in;
                1'b1: Q<=r_in;
            endcase        
        end
    
endmodule

12..Mux and DFF_2

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    
    wire p;
    always@(posedge clk)
        begin
            case(E)
                1'b0: p=Q;   //采用阻塞赋值
                1'b1: p=w;
            endcase
            
            case(L)
                1'b0: Q=p;
                1'b1: Q=R;
            endcase
            
        end
 
endmodule

13.DFFs and gates

module top_module (
    input clk,
    input x,
    output z
); 
    
    wire q1,q2,q3;
    always@(posedge clk)       
        begin          
            q1<=x^q1;
            q2<=x&(~q2);
            q3<=x|(~q3);          
        end
    assign z=~(q1|q2|q3);//不受时钟影响
endmodule

14.Create circuit from truth table

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
      
    always@(posedge clk)
       begin
           case({j,k})
               2'b00: Q<=Q;
               2'b01: Q<=0;
               2'b10: Q<=1;
               2'b11: Q<=~Q;
           endcase
       end
endmodule

15.Detect an edge

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    
    reg [7:0] p;
    always@(posedge clk)
        begin
           p<=in;
           pedge<=~p&in;  //原来为0，跳变为1后，输出位才为1.即~0&1=1
        end
 
    
endmodule

16.Detect both edges

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    
    reg [7:0] p;
    always@(posedge clk)
        begin
           p<=in;
           anyedge<=p^in;
        end
 
endmodule

17.Edge capture register

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
 
    reg[31:0] p;
    
    always@(posedge clk)
        begin
           p<=in; 
        end
    
    always@(posedge clk)
        begin
            if(reset)
               out<=0;
             else
                 begin                   
                     out<=(p&~in)|out;  //捕获后，将一直保持1，只有复位才能置为0
                 end
            
        end
    
endmodule

18.Dual-edge triggered

module top_module (
    input clk,
    input d,
    output q
);
 
   reg p1,p2;
    always@(posedge clk)
        begin
           p1<=d; 
        end
    always@(negedge clk)
        begin
           p2<=d; 
        end
    assign q=clk ? p1 : p2;
    
endmodule