Circuits--Sequential--FSM--Q6b~Q2b

1. Q6b

module top_module (
    input [3:1] y,
    input w,
    output Y2);
	
    assign Y2 = ((y==3'b001|y==3'b101)&~w)|((y==3'b001|y==3'b100|y==3'b101|y==3'b010)&w);

2.Q6c

module top_module (
    input [6:1] y,
    input w,
    output Y2,
    output Y4);
    
    assign Y2 = (y[1]) & ~w;
    assign Y4 = (y[2]&w)|(y[3]&w)|(y[5]&w)|(y[6]&w);

endmodule

3.Q6

module top_module (
    input clk,
    input reset,     // synchronous reset
    input w,
    output z);
    
    parameter A = 3'd0;
    parameter B = 3'd1;
    parameter C = 3'd2;
    parameter D = 3'd3;
    parameter E = 3'd4;
    parameter F = 3'd5;
    
    reg[2:0] state;
    reg[2:0] next_state;
    
    always@(*)
        begin
            case(state)
                A:
                    begin
                        if(w) next_state = A;
                        else  next_state = B;
                    end
                 B:
                    begin
                        if(w) next_state = D;
                        else  next_state = C;
                    end
                 C:
                    begin
                        if(w) next_state = D;
                        else  next_state = E;
                    end
                 D:
                    begin
                        if(w) next_state = A;
                        else  next_state = F;
                    end
                 E:
                    begin
                        if(w) next_state = D;
                        else  next_state = E;
                    end
                 F:
                    begin
                        if(w) next_state = D;
                        else  next_state = C;
                    end
            endcase
        end
    
    always@(posedge clk)
        begin
            if(reset)
                state = A;
            else
                state = next_state;
        end
    
    assign z = (state == E | state == F);

endmodule

4.Q2a_1

module top_module (
    input clk,
    input reset,     // synchronous reset
    input w,
    output z);
    
    parameter A = 3'd0;
    parameter B = 3'd1;
    parameter C = 3'd2;
    parameter D = 3'd3;
    parameter E = 3'd4;
    parameter F = 3'd5;
    
    reg[2:0] state;
    reg[2:0] next_state;
    
    always@(*)
        begin
            case(state)
                A:
                    begin
                        if(w) next_state = B;
                        else  next_state = A;
                    end
                 B:
                    begin
                        if(w) next_state = C;
                        else  next_state = D;
                    end
                 C:
                    begin
                        if(w) next_state = E;
                        else  next_state = D;
                    end
                 D:
                    begin
                        if(w) next_state = F;
                        else  next_state = A;
                    end
                 E:
                    begin
                        if(w) next_state = E;
                        else  next_state = D;
                    end
                 F:
                    begin
                        if(w) next_state = C;
                        else  next_state = D;
                    end
            endcase
        end
    
    always@(posedge clk)
        begin
            if(reset)
                state = A;
            else
                state = next_state;
        end
    
    assign z = (state == E | state == F);

endmodule

5.Q2b_1

module top_module (
    input [5:0] y,
    input w,
    output Y1,
    output Y3
);
    
    assign Y1 = (y[0]&w);
    assign Y3 = (y[1]&~w)|(y[2]&~w)|(y[4]&~w)|(y[5]&~w);
    

endmodule

6.Q2a_2

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input [3:1] r,   // request
    output [3:1] g   // grant
); 
    
    parameter A = 2'd0;
    parameter B = 2'd1;
    parameter C = 2'd2;
    parameter D = 2'd3;
    
    reg[1:0] state;
    reg[1:0] next_state;
  
    
    always@(*)
        begin
            case(state)
                A:
                    begin
                        
                        if(r[1])
                            next_state = B;
                        else if(r[2])
                            next_state = C;
                        else if(r[3])
                            next_state = D;
                        else
                            next_state = A;
                    end
               B:       next_state = r[1] ? B : A;
               C:       next_state = r[2] ? C : A;
               D:       next_state = r[3] ? D : A;
                default: next_state = A;
            endcase
        end
    
    always@(posedge clk)
        begin
            if(~resetn)
                state <= A;
            else
                state <= next_state;
        end
    
    assign g[1] = (state == B);
    assign g[2] = (state == C);
    assign g[3] = (state == D);
endmodule

7. Q2b_2

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    
    parameter[3:0] S = 4'd0; 
    parameter[3:0] F = 4'd01; 
    parameter[3:0] XA = 4'd2; 
    parameter[3:0] XB = 4'd3; 
    parameter[3:0] XC = 4'd4;
    parameter[3:0] X1 = 4'd5;
    parameter[3:0] YA = 4'd6; 
    parameter[3:0] YB1 = 4'd7; 
    parameter[3:0] YB2 = 4'd8; 
    parameter[3:0] YC = 4'd9; 
    
    reg[3:0] state;
    reg[3:0] next_state;
    
    always@(*)
        begin
            case(state)
                S:
                    next_state = F;
                F:
                    next_state = XA;
                XA:
                    begin
                        if(x) next_state = XB;
                        else  next_state = XA;
                    end
                XB:
                    begin
                        if(x) next_state = XB;
                        else  next_state = XC;
                    end
                XC:
                    begin
                        if(x) next_state = X1;
                        else  next_state = XA;
                    end
                X1:
                    next_state = YA;
               
                YA:
                    begin
                        if(y) next_state = YB1;
                        else  next_state = YB2;
                    end
                YB2:
                    begin
                        if(y) next_state = YB1;
                        else  next_state = YC;
                    end
            endcase
        end
    
    always@(posedge clk)
        begin
            if(~resetn)
                state <= S;
            else
                state <= next_state;
        end
    
    assign f = (state == F);
    assign g = (state == X1)|(state == YA)|(state == YB1);
    
   

endmodule