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Boundary scan 流程图
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Load the Design
set_context dft -rtl
read_cell_library …/library/adk_complete.tcelllib
read_verilog …/netlist/cpu_top.v
set_current_design cpu_top -
Specify and Verify DFT Requirements
set_dft_specification_requirements -boundary_scan on
set_design_level chip
set_attribute_value tck_p -name function -value tck
set_attribute_value tdi_p -name function -value tdi
set_attribute_value tms_p -name function -value tms
set_attribute_value trst_p -name function -value trst
set_attribute_value tdo_p -name function -value tdo
set_boundary_scan_port_options ramclk_p -cell_options clock
set_boundary_scan_port_options reset_p -cell_options sample
check_design_rules
3.Create DFT Specification
set spec [create_dft_specification]
report_config_data $spec
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Process DFT Specification
process_dft_specification -
Extract ICL
extract_icl -
Create Patterns Specification
create_patterns_specification -
Run and Check Test Bench Simulations
set_simulation_library_sources -y …/library/verilog
-v …/library/pad_cells.v
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