Reset synchronizer实现同步复位异步释放

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Reset synchronizer可以实现异步复位同步释放[1]。这种复位电路可以保留异步复位设计简单的优势，又避免了异步复位释放时可能产生的亚稳态[2]。

图源[1]。
Reset synchronizer代码：

module asyn_rst_syn_release(
    input clk,
    input rst_n,
    input data_in,
    output reg data_out
);

    reg rst_n_reg_a,rst_n_reg_b;
    wire rst_n_sync;

    always @ (posedge clk or negedge rst_n)
        if (!rst_n)
            begin
                rst_n_reg_a <= 1'b0;
                rst_n_reg_b <= 1'b0;
            end
        else
            begin
                rst_n_reg_a <= 1'b1;
                rst_n_reg_b <= rst_n_reg_a;
            end

    assign rst_n_sync = rst_n_reg_b;

    always @ (posedge clk or negedge rst_n_sync)
        if (!rst_n_sync)
            data_out <= 1'b0;
        else
            data_out <= data_in;

endmodule

简单来说，Reset synchronizer在复位时与异步复位相同，但在复位释放时，会把rst_n信号打两拍，实现同步释放。（这里看不懂的话后面有testbench和波形）。
testbench：

`timescale 1ns / 1ps

module asyn_rst_syn_release_tb();

    reg clk;
    reg rst_n;
    reg data_in = 1;
    wire data_out;

    initial 
        begin
            clk = 1;
            #200 $stop;
        end

    initial 
        fork
            rst_n = 1;
            #12 rst_n = 0;
            #20 rst_n = 1;
            //#32 rst_n = 0;
            //#42 rst_n = 1;

            #112 rst_n = 0;
            #114 rst_n = 1;
            //#132 rst_n = 0;
            //#138 rst_n = 1;
        join
    

    always #10 clk =~clk;

    asyn_rst_syn_release asyn_rst_syn_release0(
        .clk(clk),
        .rst_n(rst_n),
        .data_in(data_in),
        .data_out(data_out)
        );

endmodule

波形：

可以看到，rst_n = 0时，立即触发异步复位，data_out = 0；而当rst_n重新置高后，打了两拍才同步释放，这时，rst_n_sync已经稳定在高电平了，此时采样就不会出现亚稳态的问题。
这也是为什么需要两个寄存器，如果只打一拍，rst_n_sync置高时刚好发生在clk上升沿，此时可能会发生亚稳态。关于这一点，Clifford E.Cummings在论文中是这样解释的：[1]

The first flip-flop of the reset synchronizer does have potential metastability problems because the input is tied high, the output has been asynchronously reset to a 0 and the reset could be removed within the specified reset recovery time of the flip-flop (the reset may go high too close to the rising edge of the clock input to the same flip-flop). This is why the second flip-flop is required.
The second flip-flop of the reset synchronizer is not subject to recovery time metastability because the input and output of the flip-flop are both low when reset is removed. There is no logic differential between the input and output of the flip-flop so there is no chance that the output would oscillate between two different logic values.

代码RTL电路：

最后，我产生了一个问题，按这样来说，当复位释放在clk上升沿附近时，同步复位是否也会产生亚稳态？这个问题在[1]中同样有答案：

A different but similar problem exists for synchronous resets if these spurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is true of any data input that violates setup requirements).

When a synchronous reset is being used, then both the leading and trailing edges of the reset must be away from the active edge of the clock.

参考：
[1]Clifford E.Cummings, Don Mills, and Steve Golson. Asynchronous & Synchronous Reset Design Techniques - Part Deux[C]SNUG (Synopsys Users Group) 2003User papers
下载：http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf
[2]EDA先锋工作室编著.轻松成为设计高手 Verilog HDL实用精解[M].北京航空航天大学出版社,2012.

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