SelectIO（参考ug471）

SelectIO

常用原语

IBUF/IBUFG

• Primitive：Input Buffer
• 工具自动插入，普通引脚输入插入 IBUF，时钟引脚输入插入 IBUFG
• IBUF_LOW_PWR、IOSTANDARD属性可以单独通过 XDC 进行约束

IBUF #(
  .IBUF_LOW_PWR("TRUE"),  // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
  .IOSTANDARD("DEFAULT")  // Specify the input I/O standard
) IBUF_inst (
  .O(O),     // Buffer output
  .I(I)      // Buffer input (connect directly to top-level port)
);

IBUFDS/IBUFGDS

• Primitive：Differential Signaling Input Buffer

• 真值表

  

IBUFDS #(
  .DIFF_TERM("FALSE"),       // Differential Termination
  .IBUF_LOW_PWR("TRUE"),     // Low power="TRUE", Highest performance="FALSE" 
  .IOSTANDARD("DEFAULT")     // Specify the input I/O standard
) IBUFDS_inst (
  .O(O),  // Buffer output
  .I(I),  // Diff_p buffer input (connect directly to top-level port)
  .IB(IB) // Diff_n buffer input (connect directly to top-level port)
);

IOBUF

• Primitive: Bi-Directional Buffer

• 真值表

  

IOBUF #(
  .DRIVE(12), // Specify the output drive strength
  .IBUF_LOW_PWR("TRUE"),  // Low Power - "TRUE", High Performance = "FALSE" 
  .IOSTANDARD("DEFAULT"), // Specify the I/O standard
  .SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
  .O(O),     // Buffer output
  .IO(IO),   // Buffer inout port (connect directly to top-level port)
  .I(I),     // Buffer input
  .T(T)      // 3-state enable input, high=input, low=output
);

IOBUFDS

• Primitive: 3-State Differential Signaling I/O Buffer with active-Low Output Enable

IOBUFDS #(
  .DIFF_TERM("FALSE"),     // Differential Termination ("TRUE"/"FALSE")
  .IBUF_LOW_PWR("TRUE"),   // Low Power - "TRUE", High Performance = "FALSE" 
  .IOSTANDARD("BLVDS_25"), // Specify the I/O standard
  .SLEW("SLOW")            // Specify the output slew rate
) IOBUFDS_inst (
  .O(O),     // Buffer output
  .IO(IO),   // Diff_p inout (connect directly to top-level port)
  .IOB(IOB), // Diff_n inout (connect directly to top-level port)
  .I(I),     // Buffer input
  .T(T)      // 3-state enable input, high=input, low=output
);

OBUF

• Primitive: Output Buffer
• 工具自动插入

OBUF #(
  .DRIVE(12),   // Specify the output drive strength
  .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
  .SLEW("SLOW") // Specify the output slew rate
) OBUF_inst (
  .O(O),     // Buffer output (connect directly to top-level port)
  .I(I)      // Buffer input
);

OBUFDS

• Primitive: Differential Signaling Output Buffer

OBUFDS #(
  .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
  .SLEW("SLOW")           // Specify the output slew rate
) OBUFDS_inst (
  .O(O),     // Diff_p output (connect directly to top-level port)
  .OB(OB),   // Diff_n output (connect directly to top-level port)
  .I(I)      // Buffer input
);

OBUFT

• Primitive: 3-State Output Buffer with Active Low Output Enable

• 真值表

  

OBUFT #(
  .DRIVE(12),   // Specify the output drive strength
  .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
  .SLEW("SLOW") // Specify the output slew rate
) OBUFT_inst (
  .O(O),     // Buffer output (connect directly to top-level port)
  .I(I),     // Buffer input
  .T(T)      // 3-state enable input
);

OBUFTDS

• Primitive: 3-State Output Buffer with Differential Signaling, Active-Low Output Enable

• 真值表

  

OBUFTDS #(
  .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
  .SLEW("SLOW")           // Specify the output slew rate
) OBUFTDS_inst (
  .O(O),     // Diff_p output (connect directly to top-level port)
  .OB(OB),   // Diff_n output (connect directly to top-level port)
  .I(I),     // Buffer input
  .T(T)      // 3-state enable input
);

常用 IO 约束

PACKAGE_PIN

• 约束引脚位置

• 适用对象：Ports

• XDC 语法：

  set_property PACKAGE_PIN <pin name> [get_ports <port>]
  

IOSTANDARD

• 约束引脚电平标准

• 适用对象：

  • Ports (get_ports)：Any port - Define the IOSTANDARD in the RTL source of I/O Ports, or as XDC constraints for port cells

• XDC 语法：

  set_property IOSTANDARD <IO standard> [get_ports <ports>]
  

• The IOSTANDARD default for single-ended I/O is LVCMOS18, for differential I/Os the default is DIFF_HSTL_II_18

• 支持的所有电平标准

  

  

  

IBUF_LOW_PWR

• 适用对象：

  • Input ports (get_ports) with a VREF-based I/O Standard such as SSTL or HSTL or a differential standard such as LVDS or DIFF_HSTL

• 属性值：TRUE | FALSE

  • TRUE（Default）：low power mode，体现在功耗估算报告中
  • FALSE：high performance mode，体现在通过 input buffer 的输入延迟，可通过静态时序报告查看延迟时间

• XDC 语法：

  set_property IBUF_LOW_PWR TRUE [get_ports port_name]
  

• 适用对象：Input ports

SLEW

• 输出压摆率(Output Slew Rate)，即调节信号的转换速率。压摆率会影响信号的上升沿和下降沿。有三种压摆率设置：FAST，MEDIUM 和 SLOW。较高的摆率可为高性能系统提供高速转换（如高频存储器接口），功耗也会增加，而较低的摆率可降低系统噪声和串扰，但会在上升沿和下降沿增加标称延迟。默认情况下， Vivado 软件将I/O管脚设置为 SLOW 摆率

• 适用对象：

  • Ports (get_ports)：Output or bidirectional ports connected
  • Cells (get_cells)：Output Buffers (all OBUF variants)

• 属性值：SLOW | MEDIUM | FAST

  • SLOW （Default）
  • MEDIUM：for UltraScale architecture, only available on high-performance (HP) I/Os
  • FAST

• XDC 语法：

  set_property SLEW value [get_ports port_name]
  

DRIVE

• Output Drive Strength，设置 IO 的驱动能力

• 适用对象：

  • Ports (get_ports) ：Output or bidirectional ports connected to output buffers

• 属性值：

• XDC 语法：

  set_property DRIVE value [get_ports port_name]
  

PULLTYPE

• 适用对象：

  • Ports (get_ports)：Apply to any top-level port

• 属性值：

  • KEEPER：Use a keeper circuit to preserve the value on the net connected to the specified port
  • PULLDOWN：Use a pulldown circuit to avoid signal floating when not being driven
  • PULLUP：Use a pullup circuit to avoid signal floating when not being driven
  • {}：(NULL) Do not use a keeper, pulldown, or pullup circuit (default)

• XDC 语法：

  set_property PULLTYPE {KEEPER|PULLDOWN|PULLUP|{}} [get_ports port_name]
  

DIFF_TERM

• 7系列 FPGA 内置差分终端电阻100Ω，可通过该属性进行使能，一般高频信号需要加终端电阻来减少反射波和干扰原信号，对于低频信号则不需要。

• 如果要使用内部终端电阻，LVDS 电平标准信号对应 I/O BANK 的 VCCO 电压必须是 1.8V，而其他电平标准信号对应 I/O BANK 的 VCCO 电压必须是 2.5V，否则只能使用外部终端电阻

• 适用对象（7系列 FPGA）：

  • Ports (get_ports)：Input or bidirectional ports connected to a differential input buffer
  • Applicable to elements using one of the following IOSTANDARDs:
    • LVDS, LVDS_25, MINI_LVDS_25
    • PPDS_25
    • RSDS_25

• 属性值：

  • TRUE：Differential termination is enabled
  • FALSE：Differential termination is disabled (default)

• XDC 语法：

  set_property DIFF_TERM TRUE [get_ports CLK_p]
  

DIFF_TERM_ADV

• UltraScale FPGA 内置差分终端电阻100Ω，可通过该属性进行使能，一般高频信号需要加终端电阻来减少反射波和干扰原信号，对于低频信号则不需要。

• 如果要使用内部终端电阻，HP I/O BANK 的 VCCO 电压必须是 1.8V，而HR I/O BANK 的 VCCO 电压必须是 2.5V，否则只能使用外部终端电阻

• 适用对象（UltraScale FPGA ）：

  • Ports (get_ports)：Input or bidirectional ports connected to a differential input buffer
  • Applicable to elements using one of the following IOSTANDARDs:
    • LVDS, LVDS_25, MINI_LVDS_25, SUB_LVDS
    • PPDS_25
    • RSDS_25
    • SLVS_400_25, and SLVS_400_18

• 属性值：

  • TERM_100：Utilize the 100Ω on-chip differential termination
  • TERM_NONE：Do not utilize the on-chip differential termination (default)

• XDC 语法：

  set_property DIFF_TERM_ADV TERM_100 [get_ports CLK_p]
  

IOB

• 将寄存器放置在 IOB

• 适用对象：

  • Ports (get_ports) ：Any port connected to a register

• 属性值：

  • TRUE：Place a connected register into the I/O Block
  • FALSE：Do not place the specified register into the I/O Block (default)

• XDC 语法：

  set_property IOB TRUE [get_ports ACK]
  

SelectIO 逻辑资源

HR和HP I/O Banks 区别

ILOGIC

结构图

• ILOGICE2 和 ILOGICE3 功能和对外端口一样，区别在于：
  • ILOGICE3 位于 HR I/O banks，且有 ZHOLD（zero hold delay element）
  • ILOGICE2 位于 HP I/O banks，但没有 ZHOLD

IDDR

原语

// IDDR: Input Double Data Rate Input Register with Set, Reset
//       and Clock Enable.
//       Kintex-7
// Xilinx HDL Language Template, version 2020.1

IDDR #(
  .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE" 
                                  //    or "SAME_EDGE_PIPELINED" 
  .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
  .INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
  .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
) IDDR_inst (
  .Q1(Q1), // 1-bit output for positive edge of clock
  .Q2(Q2), // 1-bit output for negative edge of clock
  .C(C),   // 1-bit clock input
  .CE(CE), // 1-bit clock enable input
  .D(D),   // 1-bit DDR data input
  .R(R),   // 1-bit reset, active high
  .S(S)    // 1-bit set, active high
);

// End of IDDR_inst instantiation

OPPOSITE_EDGE Mode

SAME_EDGE Mode

SAME_EDGE_PIPELINED Mode

注：更详细 ILOGIC 时序图见 ug471 “ILOGIC Timing Models”。

IDELAY

概述

Every I/O block contains a programmable delay primitive called IDELAYE2. The IDELAY can be connected to an ILOGICE2/ISERDESE2 or ILOGICE3/ISERDESE2 block. IDELAYE2 is a 31-tap, wraparound, delay primitive with a calibrated tap resolution. The tap delay resolution is contiguously calibrated by the use of an IDELAYCTRL reference clock from the range specified in the 7 series FPGA data sheets.

原语

// IDELAYE2: Input Fixed or Variable Delay Element
//           Kintex-7
// Xilinx HDL Language Template, version 2020.1

IDELAYE2 #(
  .CINVCTRL_SEL("FALSE"),          // Enable dynamic clock inversion (FALSE, TRUE)
  .DELAY_SRC("IDATAIN"),           // Delay input (IDATAIN, DATAIN)
  .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
  .IDELAY_TYPE("FIXED"),           // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
  .IDELAY_VALUE(0),                // Input delay tap setting (0-31)
  .PIPE_SEL("FALSE"),              // Select pipelined mode, FALSE, TRUE
  .REFCLK_FREQUENCY(200.0),        // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
  .SIGNAL_PATTERN("DATA")          // DATA, CLOCK input signal
)
IDELAYE2_inst (
  .CNTVALUEOUT(CNTVALUEOUT), // 5-bit output: Counter value output
  .DATAOUT(DATAOUT),         // 1-bit output: Delayed data output
  .C(C),                     // 1-bit input: Clock input
  .CE(CE),                   // 1-bit input: Active high enable increment/decrement input
  .CINVCTRL(CINVCTRL),       // 1-bit input: Dynamic clock inversion input
  .CNTVALUEIN(CNTVALUEIN),   // 5-bit input: Counter value input
  .DATAIN(DATAIN),           // 1-bit input: Internal delay data input
  .IDATAIN(IDATAIN),         // 1-bit input: Data input from the I/O
  .INC(INC),                 // 1-bit input: Increment / Decrement tap delay input
  .LD(LD),                   // 1-bit input: Load IDELAY_VALUE input
  .LDPIPEEN(LDPIPEEN),       // 1-bit input: Enable PIPELINE register to load data input
  .REGRST(REGRST)            // 1-bit input: Active-high reset tap-delay input
);

// End of IDELAYE2_inst instantiation

参数

• IDELAY_TYPE Attribute

  The IDELAY_TYPE attribute sets the type of delay used.

  • When the IDELAY_TYPE attribute is set to FIXED, the tap-delay value is fixed at the number of taps determined by the IDELAY_VALUE attribute setting. This value is preset and cannot be changed after configuration.

  • When the IDELAY_TYPE attribute is set to VARIABLE, the variable tap delay is selected. The tap delay can be incremented by setting CE = 1 and INC = 1, or decremented by CE = 1 and INC = 0. The increment/decrement operation is synchronous to C.

  • When the IDELAY_TYPE attribute is set to VAR_LOAD or VAR_LOAD_PIPE, the variable tap delay can be changed and dynamically loaded. The tap delay can be incremented by setting CE = 1 and INC = 1, or decremented by CE = 1 and INC = 0. The increment/ decrement operation is synchronous to C. The LD pin in this mode loads the value presented on CNTVALUEIN in VAR_LOAD mode or the value previously written to the pipeline register in VAR_LOAD_PIPE mode. This allows the tap value to be dynamically set.

• IDELAY_VALUE Attribute

  The IDELAY_VALUE attribute specifies the initial number of tap delays. The possible values are any integer from 0 to 31. The default value is zero. The value of the tap delay reverts to IDELAY_VALUE when the tap delay is reset (by asserting the LD pin). In VARIABLE mode this attribute determines the initial setting of the delay line. In VAR_LOAD or VAR_LOAD_PIPE mode, this attribute is not used, and the initial value of the delay line is therefore always zero.

• HIGH_PERFORMANCE_MODE Attribute

  When TRUE, this attribute reduces the output jitter. This reduction in jitter results in a slight increase in power dissipation from the IDELAYE2 primitive.

• SIGNAL_PATTERN Attribute

  Clock and data signals have different electrical profiles and therefore accumulate different amounts of jitter in the IDELAY chain. By setting the SIGNAL_PATTERN attribute, the user enables timing analyzer to account for jitter appropriately when calculating timing. A clock signal is periodic in nature and does not have long sequences of consecutive ones or zeroes, while data is random in nature and can have long and short sequences of ones and zeroes.

端口

• Data Input from the IOB - IDATAIN

  The IDATAIN input is driven by its associated IOB. IDELAY can drive data to either an ILOGICE2/ISERDESE2 or ILOGICE3/ISERDESE2 block, directly into the FPGA logic, or to both through the DATAOUT port with a delay set by the IDELAY_VALUE.

• Data Input from the FPGA Logic - DATAIN

  The DATAIN input is directly driven by the FPGA logic providing a logic accessible delay line. The data is driven back into the FPGA logic through the DATAOUT port with a delay set by the IDELAY_VALUE. DATAIN can be locally inverted. The data cannot be driven to an IOB.

• Data Output - DATAOUT

  Delayed data from the two data input ports. DATAOUT can drive to either an ILOGICE2/ ISERDESE2 or ILOGICE3/ISERDESE2 block, directly into the FPGA logic, or to both.

• Clock Input - C

  All control inputs to IDELAYE2 primitive (REGRST, LD, CE, and INC) are synchronous to the clock input ©. A clock must be connected to this port when IDELAY is configured in VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE mode. C can be locally inverted, and must be supplied by a global or regional clock buffer. If the ODELAYE2 primitive is used in the same I/O bank as the IDELAYE2 primitive, C must use the same clock net for both primitives.

• Module Load - LD

  • When in VARIABLE mode, the IDELAY load port, LD, loads the value set by the IDELAY_VALUE attribute. The default value of the IDELAY_VALUE attribute is zero. When the default value is used, the LD port acts as an asynchronous reset for the ILDELAY. The LD signal is an active-High signal and is synchronous to the input clock signal ©.

  • When in VAR_LOAD mode, the IDELAY load port, LD, loads the value set by the CNTVALUEIN. The value present at CNTVALUEIN[4:0] will be the new tap value. When in VAR_LOAD_PIPE mode, the IDELAY load port LD loads the value currently in the pipeline register. The value present in the pipeline register will be the new tap value.

• C Pin Polarity Switch - CINVCTRL

  The CINVCTRL pin is used for dynamically switching the polarity of the C pin. This is for use in applications when glitches are not an issue. When switching the polarity, do not use IDELAY control pins for two clock cycles.

• Count Value In - CNTVALUEIN

  The CNTVALUEIN pins are used for dynamically switching the loadable tap value.

• Count Value Out - CNTVALUEOUT

  The CNTVALUEOUT pins are used for reporting the loaded tap value.

• Pipeline Register Load - LDPIPEEN

  When High, this input loads the pipeline register with the value currently on the CNTVALUEIN pins.

• Pipeline Register Reset - REGRST

  When high, this input resets the pipeline register to all zeroes.

• Increment/Decrement Signals - CE, INC

  The increment/decrement is controlled by the enable signal (CE). This interface is only available when the IDELAY is in VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE mode.

  As long as CE remains High, IDELAY will increment or decrement by T_{IDELAYRESOLUTION} every clock © cycle. The state of INC determines whether IDELAY will increment or decrement; INC = 1 increments, INC = 0 decrements, synchronously to the clock ©. If CE is Low the delay through IDELAY will not change regardless of the state of INC.

  When CE goes High, the increment/decrement operation begins on the next positive clock edge. When CE goes Low, the increment/decrement operation ceases on the next positive clock edge.

  The programmable delay taps in the IDELAYE2 primitive wrap-around. When the last tap delay is reached (tap 31) a subsequent increment function will return to tap 0. The same applies to the decrement function: decrementing from zero moves to tap 31.

  The pipeline register functionality in VAR_LOAD_PIPE mode is extremely useful in bus structure designs. Individual delays can be (pipeline) loaded one at a time using LDPIPEEN and then all delays updated to their new values at the same time using the LD pin.

四种模式

• Fixed delay mode (IDELAY_TYPE = FIXED)

  延迟由参数 IDELAY_VALUE 决定，配置后不可改变。该模式必须例化 IDELAYCTRL 原语。

• Variable delay mode (IDELAY_TYPE = VARIABLE)

  该模式必须例化 IDELAYCTRL 原语。
  

• Loadable variable delay mode (IDELAY_TYPE = VAR_LOAD)

  该模式下忽略 IDELAY_VALUE 参数，且必须例化 IDELAYCTRL 原语。

• IDELAY_TYPE = VAR_LOAD_PIPE

  主要操作同 VAR_LOAD 模式，但不清楚所谓的 pipeline register 是指哪个寄存器？

时序

XDC约束

通过分组将 IDELAY/ODELAY 和 IDELAYCTRL 关联

set_property IODELAY_GROUP IO_DLY1 [get_cells MY_IDELAYCTRL_inst]
set_property IODELAY_GROUP IO_DLY1 [get_cells MY_IDELAY_inst]
set_property IODELAY_GROUP IO_DLY1 [get_cells MY_ODELAY_inst]

IDELAYCTRL

• 如果例化 IDELAYE2 or ODELAYE2 原语，则必须同时例化 IDELAYCTRL 原语

原语

-- IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
--             Kintex-7
-- Xilinx HDL Language Template, version 2020.1

IDELAYCTRL_inst : IDELAYCTRL
port map (
  RDY => RDY,       -- 1-bit output: Ready output
  REFCLK => REFCLK, -- 1-bit input: Reference clock input
  RST => RST        -- 1-bit input: Active high reset input
);

-- End of IDELAYCTRL_inst instantiation

端口

• RST - Reset

  The reset input pin (RST) is an active-High asynchronous reset. To ensure proper IDELAY and ODELAY operation, IDELAYCTRL must be reset after configuration and the REFCLK signal is stable. A reset pulse width T_{IDELAYCTRL_RPW} is required.

• REFCLK - Reference Clock

  The reference clock (REFCLK) provides a time reference to IDELAYCTRL to calibrate all IDELAY and ODELAY modules in the same region. This clock must be driven by a global or horizontal clock buffer (BUFG or BUFH). REFCLK must be F_{IDELAYCTRL_REF} ± the specified ppm tolerance (IDELAYCTRL_REF_PRECISION) to guarantee a specified IDELAY and ODELAY resolution (T_{IDELAYRESOLUTION}). REFCLK can be supplied directly from a user-supplied source or the MMCM and must be routed on a global clock buffer.

• RDY - Ready

  The ready (RDY) signal indicates when the IDELAY and ODELAY modules in the specific region are calibrated. The RDY signal is deasserted if REFCLK is held High or Low for more than one clock period. If RDY is deasserted Low, the IDELAYCTRL module must be reset. The implementation tools allow RDY to be unconnected/ignored. Figure 2-15 illustrates the timing relationship between RDY and RST.

时序

位置

IDELAYCTRL modules exist in every I/O column in every clock region. An IDELAYCTRL module calibrates all the IDELAYE2 and ODELAYE2 modules within its clock region.

OLOGIC

结构图

ODDR

原语

// ODDR: Output Double Data Rate Output Register with Set, Reset
//       and Clock Enable.
//       Kintex-7
// Xilinx HDL Language Template, version 2020.1

ODDR #(
  .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
  .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
  .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
) ODDR_inst (
  .Q(Q),   // 1-bit DDR output
  .C(C),   // 1-bit clock input
  .CE(CE), // 1-bit clock enable input
  .D1(D1), // 1-bit data input (positive edge)
  .D2(D2), // 1-bit data input (negative edge)
  .R(R),   // 1-bit reset
  .S(S)    // 1-bit set
);

// End of ODDR_inst instantiation

OPPOSITE_EDGE Mode

SAME_EDGE Mode

注：更详细 OLOGIC 时序图见 ug471 “OLOGIC Timing Models”。

ODELAY

概述

Every HP I/O block contains a programmable absolute delay primitive called ODELAYE2. The ODELAY can be connected to an OLOGICE2/OSERDESE2 block. ODELAY is a 31-tap, wraparound, delay primitive with a calibrated tap resolution. Refer to the 7 series FPGA data sheets for delay values. It can be applied to the combinatorial output path or registered output path. It can also be accessed directly from the FPGA logic. ODELAY allows outgoing signals to be delayed on an individual basis. The tap delay resolution is varied by selecting an IDELAYCTRL reference clock from the range specified in the 7 series FPGA data sheets.

原语

// ODELAYE2: Output Fixed or Variable Delay Element
//           Kintex-7
// Xilinx HDL Language Template, version 2020.1

ODELAYE2 #(
  .CINVCTRL_SEL("FALSE"),          // Enable dynamic clock inversion (FALSE, TRUE)
  .DELAY_SRC("ODATAIN"),           // Delay input (ODATAIN, CLKIN)
  .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
  .ODELAY_TYPE("FIXED"),           // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
  .ODELAY_VALUE(0),                // Output delay tap setting (0-31)
  .PIPE_SEL("FALSE"),              // Select pipelined mode, FALSE, TRUE
  .REFCLK_FREQUENCY(200.0),        // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
  .SIGNAL_PATTERN("DATA")          // DATA, CLOCK input signal
)
ODELAYE2_inst (
  .CNTVALUEOUT(CNTVALUEOUT), // 5-bit output: Counter value output
  .DATAOUT(DATAOUT),         // 1-bit output: Delayed data/clock output
  .C(C),                     // 1-bit input: Clock input
  .CE(CE),                   // 1-bit input: Active high enable increment/decrement input
  .CINVCTRL(CINVCTRL),       // 1-bit input: Dynamic clock inversion input
  .CLKIN(CLKIN),             // 1-bit input: Clock delay input
  .CNTVALUEIN(CNTVALUEIN),   // 5-bit input: Counter value input
  .INC(INC),                 // 1-bit input: Increment / Decrement tap delay input
  .LD(LD),                   // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
                             // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN

  .LDPIPEEN(LDPIPEEN),       // 1-bit input: Enables the pipeline register to load data
  .ODATAIN(ODATAIN),         // 1-bit input: Output delay data input
  .REGRST(REGRST)            // 1-bit input: Active-high reset tap-delay input
);

// End of ODELAYE2_inst instantiation

参数

• ODELAY_TYPE Attribute

  • When set to FIXED, the tap-delay value is fixed at the number of taps determined by the ODELAY_VALUE attribute setting. This value is preset and cannot be changed after configuration.

  • When set to VARIABLE, the variable tap delay is selected. The tap delay can be incremented by setting CE = 1 and INC = 1, or decremented by CE = 1 and INC = 0. The increment/decrement operation is synchronous to C.

  • When set to VAR_LOAD or VAR_LOAD_PIPE, the variable tap delay can be changed and dynamically loaded. The tap delay can be incremented by setting CE = 1 and INC = 1, or decremented by CE = 1 and INC = 0. The increment/decrement operation is synchronous to C. The LD pin in VAR_LOAD mode loads the value presented on CNTVALUEIN. This allows the tap value to be dynamically set. When in VAR_LOAD_PIPE mode, the LD pin enables the current value in the pipeline register to be loaded into the output delay.

• ODELAY_VALUE Attribute

  The ODELAY_VALUE attribute specifies tap delays. The possible values are any integer from 0 to 31. The default value is zero. The value of the tap delay reverts to ODELAY_VALUE when the tap delay is reset by asserting the LD signal. In VAR_LOAD or VAR_LOAD_PIPE mode, this attribute is assumed to be zero.

• HIGH_PERFORMANCE_MODE Attribute

  When TRUE, this attribute reduces the output jitter. This reduction in jitter results in a slight increase in power dissipation from the ODELAYE2 primitive.

• SIGNAL_PATTERN Attribute

  Clock and data signals have different electrical profiles and therefore accumulate different amounts of jitter in the ODELAY chain. By setting the SIGNAL_PATTERN attribute, the user enables timing analyzer to account for jitter appropriately when calculating timing. A clock signal is periodic in nature and does not have long sequences of consecutive ones or zeroes, while data is random in nature and can have long and short sequences of ones and zeroes.

端口

• Data Input from the FPGA OLOGICE2/OSERDESE2 - ODATAIN

  The ODATAIN input is driven by OLOGICE2/OSERDESE2. The ODATAIN drives the DATAOUT port which is connected to an IOB with a delay set by the ODELAY_VALUE.

• Clock Input from Clock Buffer - CLKIN

  The CLKIN input is driven from clock buffers (BUFIO, BUFG or BUFR). This clock is then delayed by a value set to ODELAY_VALUE and output though the DATAOUT and output buffer (OBUFT or OBUFTDS). When an IOBUF is used, the delayed clock can be routed back to the FPGA logic.

  Caution: Be aware that a package pin of the FPGA is used when using an IOBUF to route a clock back into the FPGA.

• Data Output - DATAOUT

  Delayed data from one of the two data input ports. DATAOUT connects to the IOB.

• Clock Input - C

  All control inputs to ODELAYE2 primitive (LD, CE, and INC) are synchronous to the clock input ©. A clock must be connected to this port when ODELAY is configured in VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE mode. C can be locally inverted, and must be supplied by a global or regional clock buffer. This clock must be connected to the same clock as used in the SelectIO logic resources. For example, when using the OSERDESE2, C is connected to the same clock as CLKDIV. If the IDELAYE2 primitive is used in the same I/O bank as the ODELAYE2 primitive, C must use the same clock net for both primitives.

• Module Load - LD

  • When in VARIABLE mode, the ODELAY load port, LD, loads the delay primitive to a value set by the ODELAY_VALUE attribute. If these attributes are not specified, a value of zero is assumed. The LD signal is an active-High signal and is synchronous to the input clock signal ©.
  • When in VAR_LOAD mode, the ODELAY load port, LD, loads the delay primitive to a value set by the CNTVALUEIN. The value present at CNTVALUEIN[4:0] will be the new tap value. As a result of this functionality the ODELAY_VALUE attribute is ignored.
  • When in VAR_LOAD_PIPE mode, the IDELAY load port, LD, loads the value currently in the pipeline register. The value present in the pipeline register will be the new tap value.

• Pipeline Register Load - LDPIPEEN

  When High, this input loads the pipeline register with the value currently on the CNTVALUEIN pins.

• Pipeline Register Reset - REGRST

  When high, this input resets the pipeline register to all zeroes.

• C Pin Polarity Switch - CINVCTRL

  The CINVCTRL pin is used for dynamically switching the polarity of C pin. This is for use in applications when glitches are not an issue. When switching the polarity, do not use ODELAY control pins for two clock cycles.

• Count Value In - CNTVALUEIN

  The CNTVALUEIN pins are used together with the LD pin for dynamically switching the loadable tap value.

• Count Value Out - CNTVALUEOUT

  The CNTVALUEOUT pins are used for reporting the loaded tap value.

• Increment/Decrement Signals - CE, INC

  The increment/decrement is controlled by the enable signal (CE). This interface is only available when ODELAY is in VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE mode.

  As long as CE remains High, ODELAY will increment or decrement by T_{IDELAYRESOLUTION} every clock © cycle. The state of INC determines whether ODELAY will increment or decrement; INC = 1 increments, INC = 0 decrements, synchronously to the clock ©. If CE is Low the delay through ODELAY will not change regardless of the state of INC.

  When CE goes High, the increment/decrement operation begins on the next positive clock cycle. When CE goes Low, the increment/decrement operation ceases on the next positive clock edge.

  The programmable delay taps in the ODELAYE2 primitive wrap-around. When the end of the delay tap is reached (tap 31) a subsequent increment function will return to tap 0. The same applies to the decrement function: decrementing below zero moves to tap 31.

  The pipeline register functionality in VAR_LOAD_PIPE mode is extremely useful in bus structure designs. Individual delays might be (pipeline) loaded one at a time using LDPIPEEN and then all delays updated to their new values at the same time using the LD pin.

四种模式

• Fixed delay mode (ODELAY_TYPE = FIXED)

  延迟由参数 ODELAY_VALUE 决定，配置后不可改变。该模式必须例化 IDELAYCTRL 原语。

• Variable delay mode (ODELAY_TYPE = VARIABLE)

  该模式必须例化 IDELAYCTRL 原语。

• Loadable variable delay mode (ODELAY_TYPE = VAR_LOAD)

  该模式下忽略 ODELAY_VALUE 参数，且必须例化 IDELAYCTRL 原语。

• ODELAY_TYPE = VAR_LOAD_PIPE

  主要操作同 VAR_LOAD 模式，但不清楚所谓的 pipeline register 是指哪个寄存器？

时序

XDC约束

通过分组将 IDELAY/ODELAY 和 IDELAYCTRL 关联

set_property IODELAY_GROUP IO_DLY1 [get_cells MY_IDELAYCTRL_inst]
set_property IODELAY_GROUP IO_DLY1 [get_cells MY_IDELAY_inst]
set_property IODELAY_GROUP IO_DLY1 [get_cells MY_ODELAY_inst]

ISERDESE2

结构图

每个 I/O tile 包含两个 ISERDESE2，两个间可以级联使用。

原语

-- ISERDESE2: Input SERial/DESerializer with Bitslip
--            Kintex-7
-- Xilinx HDL Language Template, version 2020.1

ISERDESE2_inst : ISERDESE2
generic map (
  DATA_RATE => "DDR",           -- DDR, SDR
  DATA_WIDTH => 4,              -- Parallel data width (2-8,10,14)
  DYN_CLKDIV_INV_EN => "FALSE", -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
  DYN_CLK_INV_EN => "FALSE",    -- Enable DYNCLKINVSEL inversion (FALSE, TRUE)
  INIT_Q1 => '0',               -- INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
  INIT_Q2 => '0',
  INIT_Q3 => '0',
  INIT_Q4 => '0',
  INTERFACE_TYPE => "MEMORY",   -- MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
  IOBDELAY => "NONE",           -- NONE, BOTH, IBUF, IFD
  NUM_CE => 2,                  -- Number of clock enables (1,2)
  OFB_USED => "FALSE",          -- Select OFB path (FALSE, TRUE)
  SERDES_MODE => "MASTER",      -- MASTER, SLAVE
  SRVAL_Q1 => '0',              -- SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
  SRVAL_Q2 => '0',
  SRVAL_Q3 => '0',
  SRVAL_Q4 => '0'
)
port map (
  O => O,                       -- 1-bit output: Combinatorial output
  -- Q1 - Q8: 1-bit (each) output: Registered data outputs
  Q1 => Q1,
  Q2 => Q2,
  Q3 => Q3,
  Q4 => Q4,
  Q5 => Q5,
  Q6 => Q6,
  Q7 => Q7,
  Q8 => Q8,
  -- SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
  SHIFTOUT1 => SHIFTOUT1,
  SHIFTOUT2 => SHIFTOUT2,
  BITSLIP => BITSLIP,           -- 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
                                -- CLKDIV when asserted (active High). Subsequently, the data seen on the
                                -- Q1 to Q8 output ports will shift, as in a barrel-shifter operation, one
                                -- position every time Bitslip is invoked (DDR operation is different from
                                -- SDR).

  -- CE1, CE2: 1-bit (each) input: Data register clock enable inputs
  CE1 => CE1,
  CE2 => CE2,
  CLKDIVP => CLKDIVP,           -- 1-bit input: TBD
  -- Clocks: 1-bit (each) input: ISERDESE2 clock input ports
  CLK => CLK,                   -- 1-bit input: High-speed clock
  CLKB => CLKB,                 -- 1-bit input: High-speed secondary clock
  CLKDIV => CLKDIV,             -- 1-bit input: Divided clock
  OCLK => OCLK,                 -- 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY" 
  -- Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
  DYNCLKDIVSEL => DYNCLKDIVSEL, -- 1-bit input: Dynamic CLKDIV inversion
  DYNCLKSEL => DYNCLKSEL,       -- 1-bit input: Dynamic CLK/CLKB inversion
  -- Input Data: 1-bit (each) input: ISERDESE2 data input ports
  D => D,                       -- 1-bit input: Data input
  DDLY => DDLY,                 -- 1-bit input: Serial data from IDELAYE2
  OFB => OFB,                   -- 1-bit input: Data feedback from OSERDESE2
  OCLKB => OCLKB,               -- 1-bit input: High speed negative edge output clock
  RST => RST,                   -- 1-bit input: Active high asynchronous reset
  -- SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
  SHIFTIN1 => SHIFTIN1,
  SHIFTIN2 => SHIFTIN2
);

-- End of ISERDESE2_inst instantiation

参数

DATA_RATE，DATA_WIDTH

• DATA_RATE 属性值：DDR (Default) | SDR

• DATA_WIDTH 属性值：默认 4

• 注：当位宽大于 8 bit，必须级联使用 ISERDESE2

DYN_CLKDIV_INV_EN，DYN_CLK_INV_EN

• 属性值：TRUE | FALSE (Default)

• 当 INTERFACE_TYPE = MEMORY_QDR 或 MEMORY_DDR3 时，可使能用于动态时钟极性切换功能。

• 时钟变化后要对 ISERDESE2 进行复位，否则可能导致数据错误。

INIT_Q1-Q4

• 属性值：0 (Default) | 1

• INIT_Q1：采集到第 1 bit 寄存器的初始值

• INIT_Q2：采集到第 2 bit 寄存器的初始值

• INIT_Q3：采集到第 3 bit 寄存器的初始值

• INIT_Q4：采集到第 4 bit 寄存器的初始值

INTERFACE_TYPE

• 属性值：MEMORY (Default) | MEMORY_DDR3 | MEMORY_QDR | OVERSAMPLE | NETWORKING

• 只支持用户使用 MEMORY，OVERSAMPLE ，NETWORKING 三种类型，其余两种只支持在 MIG 核里使用
  

• 区别：

  • OVERSAMPLE 的使用场景是啥？
  • MEMORY 使用场景为 Memory 接口

• OVERSAMPLE 接口类型设计参考：
  • xapp523-LVDS 4x Asynchronous Oversampling Using 7 Series FPGAs Application Note
• NETWORKING 接口类型设计参考：

  • xapp1017-LVDS Source Synchronous DDR Deserialization (up to 1,600 Mb/s) Application Note

  • xapp524-Serial LVDS High-Speed ADC Interface Application Note

IOBDELAY

• 属性值：NONE (Default) | IBUF | IFD | BOTH

• 对应端口
  • D：Serial Input Data from IOB）
  • DDLY：Serial Input Data from IDELAYE2

NUM_CE

• 属性值：1 | 2 (Default)
  • 1：只使用 CE1 信号
  • 2：同时使用 CE1 和 CE2 信号
• INTERFACE_TYPE 只支持用户使用 MEMORY，OVERSAMPLE ，NETWORKING 三种类型，参考 XAPP523, XAPP524, XAPP1017 用例，针对 这三种 INTERFACE_TYPE 类型 NUM_CE 都为 1，不知道什么情况下 NUM_CE 应该为 2 ？

OFB_USED （不知道什么作用？？？）

• 属性值：TRUE | FALSE (Default)

• 对应端口：

  • OFB：Serial Input Data from OSERDESE2

• 使用介绍：

  • 只有在 ISERDESE2 输出位宽大于 8 bit 时使用；
  • ISERDESE2 和 OSERDESE2 的 DATA_RATE 和 DATA_WIDTH 参数设置必须一致；
  • 只能 master OSERDESE2 与 master ISERDESE2 相连。

SERDES_MODE

• 属性值：MASTER (Default) | SLAVE

SRVAL_Q1-Q4

• 属性值：0 | 1 (Default)

• SRVAL_Q1：复位之后第 1 bit 寄存器的值

• SRVAL_Q2：复位之后第 2 bit 寄存器的值

• SRVAL_Q3：复位之后第 3 bit 寄存器的值

• SRVAL_Q4：复位之后第 4 bit 寄存器的值

端口

O

• 组合输出端口（combinatorial output port），非寄存输出
• 2 种输出数据源：来自输入端口 D 或 输入端口 DDLY

Q1-Q8

• 寄存器输出（Registered Outputs）

• 先采集到的数据在最高位

SHIFTOUT1，SHIFTOUT2，SHIFTIN1，SHIFTIN2

输出位宽大于 8 bit 时级联 ISERDESE2 连接使用。

BITSLIP

• BITSLIP 信号同步于 CLKDIV 时钟，每次只能置位 1 个时钟周期
• 每两次 BITSLIP 之间至少间隔 2 个 CLKDIV 周期
• BITSLIP 信号置位一个周期后 2 个 CLKDIV 时钟周期 （SDR 模式）或 3 个 CLKDIV 时钟周期（DDR 模式），输出数据稳定可以采集
• ISERDESE2 复位，BITSLIP 也会跟着复位
• BITSLIP 信号置位一个周期，整体数据右移 1 bit
• 下图还需置位 BITSLIP 一个周期，才能对其为 ABCD

CE1,CE2

• 时钟使能引脚，同步于 CLKDIV 时钟域
• 生成 ICE 信号驱动 FF0,FF1,FF2,FF3 寄存器的时钟使能端口
• CE 信号具体时序见下面时序章节

CLKDIVP

除了 MEMORY_DDR3 接口类型下通过 MIG 核内部赋值，其余接口类型直接赋 0

CLK，CLKB

• CLK：输入串行数据时钟

• CLKB：MEMORY_QDR 接口类型使用 MIG 核，不需要考虑如何连接。其他接口类型该信号等于 CLK 取反

CLKDIV

• 通常为 CLK 的分频信号，根据解串系数决定时钟分频系数
• 该时钟作用于：解串后并行数据，Bitslip 模块，CE 信号

OCLK，OCLKB

• OCLK

  • High-Speed Clock for Strobe-Based Memory Interfaces and Oversampling Mode

  • NETWORKING 接口类型不使用该信号，直接赋0

  • 其他接口类型该时钟频率与 OCLK 一致，但相位不同，其中 OVERSAMPLE 接口类型相对于 CLK 相移 90°

• OCLKB：OCLK 取反

DYNCLKDIVSEL，DYNCLKSEL

• 当 INTERFACE_TYPE = MEMORY_QDR 或 MEMORY_DDR3 时，可使能用于动态时钟极性切换功能。

• 时钟变化后要对 ISERDESE2 进行复位，否则可能导致数据错误

• DYNCLKDIVSEL 用于切换 CLKDIV 时钟极性

• DYNCLKSEL 用于切换 CLK，CLKB 时钟极性

D，DDLY

• D：来自 IOB 的串行输入数据

• DDLY：来自 IDELAYE2 的串行输入数据

OFB

• 只有在 ISERDESE2 输出位宽大于 8 bit 时使用；
• ISERDESE2 和 OSERDESE2 的 DATA_RATE 和 DATA_WIDTH 参数设置必须一致；
• 只能 master OSERDESE2 与 master ISERDESE2 相连。

RST

• 异步复位，同步于 CLKDIV 释放
• 复位后除了 FF0-FF3 四个寄存器的值为 SRVAL_Q1-Q4 参数值，其余均变为 0
• 只有在 CLK 和 CLKDIV 时钟稳定后才释放复位，释放后 2 个 CLKDIV 周期后输出数据才有效

时钟模型

NETWORKING

• CLK 和 CLKDIV 时钟必须相位对齐

• 时钟模型只支持以下 2 种：

  • 情况一：CLK driven by BUFIO, CLKDIV driven by BUFR
  • 情况二：CLK driven by MMCM or PLL, CLKDIV driven by CLKOUT[0:6] of same MMCM or PLL

  注：情况二（CLK 和 CLKDIV 由 MMCM 驱动），CLK 和 CLKDIV 驱动 buffer 类型必须一致，要么都为 BUFG 或者为 BUFIO + BUFR。

MEMORY

• OCLK 和 CLKDIV 必须要相位对齐，CLK 和 OCLK 没有相位要求

• 时钟模型只支持以下 3 种：

  • 情况一：CLK driven by BUFIO, OCLK driven by BUFIO, and CLKDIV driven by BUFR

  • 情况二：CLK driven by MMCM or PLL, OCLK driven by MMCM or PLL, and CLKDIV driven by CLKOUT[0:6] of same MMCM or PLL

  • 情况三：CLK driven by BUFG, OCLK driven by a BUFG, CLKDIV driven by a different BUFG

OVERSAMPLE

• 该接口类型下不使用 CLKDIV 时钟信号
• 时钟模型只支持以下 2 种：
  • 情况一：CLK and CLKB are driven by a BUFIO. OCLK and OCLKB are driven by a BUFIO that is phase shifted by 90°. The two BUFIOs are driven from a single MMCM
  • 情况二：CLK and CLKB are driven by a BUFG. OCLK and OCLKB are driven by a BUFG that is phase shifted by 90°. The BUFGs are driven from a single MMCM
  • 以上 2 种情况对应的时钟相位关系如下：
    • CLK：0°
    • OCLK：90°
    • CLKB：180°
    • OCLKB：270°

MEMORY_QDR，MEMORY_DDR3

• 该接口类型只支持使用 MIG 核

时序

延迟

• MEMORY 接口类型：通过 OCLK 阶段需要 1 个 CLKDIV 时钟周期，通过 ISERDESE2 总延迟取决于 CLK 和 OCLK 的相位关系
• NERWORKING 接口类型：总延迟 2 个 CLKDIV 时钟周期，相比 MEMORY 增加的延迟为 BITSLIP 子模块导致

• MEMORY_QDR，MEMORY_DDR3 接口类型：总延迟 2 个 CLKDIV 时钟后期

OSERDESE2

结构图

• CLK 和 CLKDIV 相位需一致
• 使用 OSERDESE2 前需先复位
• “3-State Parallel-to-Serial Conversion” 只最大支持 4 bit，该部分不可级联
• 每个 I/O tile 包含两个 OSERDESE2，两个间可以级联使用
  
  

原语

// OSERDESE2: Output SERial/DESerializer with bitslip
//            Kintex-7
// Xilinx HDL Language Template, version 2020.1

OSERDESE2 #(
  .DATA_RATE_OQ("DDR"),   // DDR, SDR
  .DATA_RATE_TQ("DDR"),   // DDR, BUF, SDR
  .DATA_WIDTH(4),         // Parallel data width (2-8,10,14)
  .INIT_OQ(1'b0),         // Initial value of OQ output (1'b0,1'b1)
  .INIT_TQ(1'b0),         // Initial value of TQ output (1'b0,1'b1)
  .SERDES_MODE("MASTER"), // MASTER, SLAVE
  .SRVAL_OQ(1'b0),        // OQ output value when SR is used (1'b0,1'b1)
  .SRVAL_TQ(1'b0),        // TQ output value when SR is used (1'b0,1'b1)
  .TBYTE_CTL("FALSE"),    // Enable tristate byte operation (FALSE, TRUE)
  .TBYTE_SRC("FALSE"),    // Tristate byte source (FALSE, TRUE)
  .TRISTATE_WIDTH(4)      // 3-state converter width (1,4)
)
OSERDESE2_inst (
  .OFB(OFB),             // 1-bit output: Feedback path for data
  .OQ(OQ),               // 1-bit output: Data path output
  // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
  .SHIFTOUT1(SHIFTOUT1),
  .SHIFTOUT2(SHIFTOUT2),
  .TBYTEOUT(TBYTEOUT),   // 1-bit output: Byte group tristate
  .TFB(TFB),             // 1-bit output: 3-state control
  .TQ(TQ),               // 1-bit output: 3-state control
  .CLK(CLK),             // 1-bit input: High speed clock
  .CLKDIV(CLKDIV),       // 1-bit input: Divided clock
  // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
  .D1(D1),
  .D2(D2),
  .D3(D3),
  .D4(D4),
  .D5(D5),
  .D6(D6),
  .D7(D7),
  .D8(D8),
  .OCE(OCE),             // 1-bit input: Output data clock enable
  .RST(RST),             // 1-bit input: Reset
  // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
  .SHIFTIN1(SHIFTIN1),
  .SHIFTIN2(SHIFTIN2),
  // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
  .T1(T1),
  .T2(T2),
  .T3(T3),
  .T4(T4),
  .TBYTEIN(TBYTEIN),     // 1-bit input: Byte group tristate
  .TCE(TCE)              // 1-bit input: 3-state clock enable
);

// End of OSERDESE2_inst instantiation

参数

DATA_RATE_OQ

• 属性值：DDR (Default) , SDR

DATA_RATE_TQ

• 属性值：DDR (Default) , BUF, SDR
  • DDR：T1-4 四个输入全部使用
  • SDR：只使用 T1 输入
  • BUF：只使用 T1 输入，OSERDESE2 只用做透传

DATA_WIDTH

• 属性值：2-8,10,14（默认 4）

注：当位宽大于 8 bit，必须级联使用 OSERDESE2

INIT_OQ，INIT_TQ

• OQ, TQ 初始输出值
• 属性值：0 (Default) | 1

SERDES_MODE

• 属性值：MASTER (Default) | SLAVE

SRVAL_OQ，SRVAL_TQ

• OQ, TQ 复位输出值
• 属性值：0 (Default) | 1

TBYTE_CTL

• 只能通过 MIG 核使用
• 属性值：FALSE (Default), TRUE

TBYTE_SRC

• 只能通过 MIG 核使用
• 属性值：FALSE (Default), TRUE

TRISTATE_WIDTH

• 三态信号转换位宽，只能设置 1 或者 4 ，大于 4 默认为 1
• 属性值：1| 4 (Default)

端口

OFB

• 2 种连接方式：
  • 作为反馈路径连接 ISERDESE2 的 OFB 端口
  • 作为 OSERDESE2 的输出连接 ODELAYE2

OQ

• 串行数据输出，D1 端口数据优先输出
• 该端口无法驱动 ODELAYE2，若需要延迟输出，则使用 OFB 作为串行数据输出

SHIFTOUT1，SHIFTOUT2，SHIFTIN1，SHIFTIN2

数据位宽大于 8 bit 时级联 OSERDESE2 连接使用。

TBYTEOUT

Byte group 3-state output

TFB

• 输出供 FPGA 内部用户使用，用于指示当前 OSEDESE2 为三态方式输出

TQ

• 三态信号输出给 IOB

CLK

• 串行数据时钟

CLKDIV

• 通常为 CLK 的分频信号，根据并串转换系数决定时钟分频系数
• 该时钟作用于：并行数据，CE 信号

D1-8

• 并行数据输入
• 级联输入
  • 从 OSERDESE2 只使用 D3-8 作为输入
  • 主从 OSERDESE2 的 DATA_WIDTH 参数必须一致

OCE

• 并串转换部分的时钟使能信号，高有效

RST

• 异步复位，所有 CLK, CLKDIV 时钟域下的输出寄存器变为 0
• 同步于 CLKDIV 时钟域释放
• 只有在 CLK 和 CLKDIV 时钟稳定后才释放复位

T1-4

• 三态控制信号输入

TBYTEIN

Byte group 3-state input

TCE

• 三态输出部分的时钟使能信号，高有效

时钟模型

• CLK 和 CLKDIV 时钟必须相位对齐

• 时钟模型只支持以下 2 种：

  • 情况一：CLK driven by BUFIO, CLKDIV driven by BUFR
  • 情况二：CLK driven by MMCM or PLL, CLKDIV driven by CLKOUT[0:6] of same MMCM or PLL

  注：情况二（CLK 和 CLKDIV 由 MMCM 驱动），CLK 和 CLKDIV 驱动 buffer 类型必须一致，要么都为 BUFG 或者为 BUFIO + BUFR。

时序

延迟

• 延迟计算原则：D1-D8 端口输入数据至第 1 个 bit 数据从 OQ 输出的时间

IO_FIFO

概述

• 每个 I/O bank 包含 4 个 IO_FIFO，1 个 IO_FIFO 定义为 1 个 byte group，每个 byte group 包含 12 个 I/O
• 1 个 IO_FIFO 包含 1 个 IN_FIFO 和 1 个 OUT_FIFO
• IO_FIFO 通常与 IOLOGIC（ISERDESE，IDDR，OSERDESE，ODDR）连接
• IO_FIFO 内部结构图如下所示：
  • 包含输入寄存器、深度 7 FIFO核、输出寄存器，可当做深度 9 的 FIFO

IN_FIFO

原语

// IN_FIFO: Input First-In, First-Out (FIFO)
//          Kintex-7
// Xilinx HDL Language Template, version 2020.1

IN_FIFO #(
  .ALMOST_EMPTY_VALUE(1),          // Almost empty offset (1-2)
  .ALMOST_FULL_VALUE(1),           // Almost full offset (1-2)
  .ARRAY_MODE("ARRAY_MODE_4_X_8"), // ARRAY_MODE_4_X_8, ARRAY_MODE_4_X_4
  .SYNCHRONOUS_MODE("FALSE")       // Clock synchronous (FALSE)
)
IN_FIFO_inst (
  // FIFO Status Flags: 1-bit (each) output: Flags and other FIFO status outputs
  .ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty
  .ALMOSTFULL(ALMOSTFULL),   // 1-bit output: Almost full
  .EMPTY(EMPTY),             // 1-bit output: Empty
  .FULL(FULL),               // 1-bit output: Full
  // Q0-Q9: 8-bit (each) output: FIFO Outputs
  .Q0(Q0),                   // 8-bit output: Channel 0
  .Q1(Q1),                   // 8-bit output: Channel 1
  .Q2(Q2),                   // 8-bit output: Channel 2
  .Q3(Q3),                   // 8-bit output: Channel 3
  .Q4(Q4),                   // 8-bit output: Channel 4
  .Q5(Q5),                   // 8-bit output: Channel 5
  .Q6(Q6),                   // 8-bit output: Channel 6
  .Q7(Q7),                   // 8-bit output: Channel 7
  .Q8(Q8),                   // 8-bit output: Channel 8
  .Q9(Q9),                   // 8-bit output: Channel 9
  // D0-D9: 4-bit (each) input: FIFO inputs
  .D0(D0),                   // 4-bit input: Channel 0
  .D1(D1),                   // 4-bit input: Channel 1
  .D2(D2),                   // 4-bit input: Channel 2
  .D3(D3),                   // 4-bit input: Channel 3
  .D4(D4),                   // 4-bit input: Channel 4
  .D5(D5),                   // 8-bit input: Channel 5
  .D6(D6),                   // 8-bit input: Channel 6
  .D7(D7),                   // 4-bit input: Channel 7
  .D8(D8),                   // 4-bit input: Channel 8
  .D9(D9),                   // 4-bit input: Channel 9
  // FIFO Control Signals: 1-bit (each) input: Clocks, Resets and Enables
  .RDCLK(RDCLK),             // 1-bit input: Read clock
  .RDEN(RDEN),               // 1-bit input: Read enable
  .RESET(RESET),             // 1-bit input: Reset
  .WRCLK(WRCLK),             // 1-bit input: Write clock
  .WREN(WREN)                // 1-bit input: Write enable
);

// End of IN_FIFO_inst instantiation

参数

端口

输入输出映射关系

OUT_FIFO

原语

//  OUT_FIFO   : In order to incorporate this function into the design,
//   Verilog   : the following instance declaration needs to be placed
//  instance   : in the body of the design code.  The instance name
// declaration : (OUT_FIFO_inst) and/or the port declarations within the
//    code     : parenthesis may be changed to properly reference and
//             : connect this function to the design.  All inputs
//             : and outputs must be connected.

//  <-----Cut code below this line---->

// OUT_FIFO: Output First-In, First-Out (FIFO) Buffer
//           Kintex-7
// Xilinx HDL Language Template, version 2020.1

OUT_FIFO #(
  .ALMOST_EMPTY_VALUE(1),          // Almost empty offset (1-2)
  .ALMOST_FULL_VALUE(1),           // Almost full offset (1-2)
  .ARRAY_MODE("ARRAY_MODE_8_X_4"), // ARRAY_MODE_8_X_4, ARRAY_MODE_4_X_4
  .OUTPUT_DISABLE("FALSE"),        // Disable output (FALSE, TRUE)
  .SYNCHRONOUS_MODE("FALSE")       // Must always be set to false.
)
OUT_FIFO_inst (
  // FIFO Status Flags: 1-bit (each) output: Flags and other FIFO status outputs
  .ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty flag
  .ALMOSTFULL(ALMOSTFULL),   // 1-bit output: Almost full flag
  .EMPTY(EMPTY),             // 1-bit output: Empty flag
  .FULL(FULL),               // 1-bit output: Full flag
  // Q0-Q9: 4-bit (each) output: FIFO Outputs
  .Q0(Q0),                   // 4-bit output: Channel 0 output bus
  .Q1(Q1),                   // 4-bit output: Channel 1 output bus
  .Q2(Q2),                   // 4-bit output: Channel 2 output bus
  .Q3(Q3),                   // 4-bit output: Channel 3 output bus
  .Q4(Q4),                   // 4-bit output: Channel 4 output bus
  .Q5(Q5),                   // 8-bit output: Channel 5 output bus
  .Q6(Q6),                   // 8-bit output: Channel 6 output bus
  .Q7(Q7),                   // 4-bit output: Channel 7 output bus
  .Q8(Q8),                   // 4-bit output: Channel 8 output bus
  .Q9(Q9),                   // 4-bit output: Channel 9 output bus
  // D0-D9: 8-bit (each) input: FIFO inputs
  .D0(D0),                   // 8-bit input: Channel 0 input bus
  .D1(D1),                   // 8-bit input: Channel 1 input bus
  .D2(D2),                   // 8-bit input: Channel 2 input bus
  .D3(D3),                   // 8-bit input: Channel 3 input bus
  .D4(D4),                   // 8-bit input: Channel 4 input bus
  .D5(D5),                   // 8-bit input: Channel 5 input bus
  .D6(D6),                   // 8-bit input: Channel 6 input bus
  .D7(D7),                   // 8-bit input: Channel 7 input bus
  .D8(D8),                   // 8-bit input: Channel 8 input bus
  .D9(D9),                   // 8-bit input: Channel 9 input bus
  // FIFO Control Signals: 1-bit (each) input: Clocks, Resets and Enables
  .RDCLK(RDCLK),             // 1-bit input: Read clock
  .RDEN(RDEN),               // 1-bit input: Read enable
  .RESET(RESET),             // 1-bit input: Active high reset
  .WRCLK(WRCLK),             // 1-bit input: Write clock
  .WREN(WREN)                // 1-bit input: Write enable
);

// End of OUT_FIFO_inst instantiation

参数

端口

输入输出映射关系

复位 IO_FIFO

• 异步复位信号输入，IO_FIFO 内部会同步于读写时钟域
• 写 IO_FIFO 前，必须先置位复位信号至少 4 个读或写时钟周期，用于复位 IO_FIFO
• 复位期间，RDEN 和 WREN 必须保持低电平
• 上电一开始就进行复位，直至读写时钟稳定。
• 若中途读或写时钟没了，同样要按照上述方法进行复位

标志信号

• EMPTY：对应输出寄存器的状态，当 EMPTY 置位，则此时输出寄存器值无效
• FULL：对应 FIFO 核和输入寄存器的状态，不关心输出寄存器状态。当 FULL 置位，表示输入寄存器和 FIFO 核都已存满数据
• ALMOST EMPTY：
  • 配置 ALMOST_EMPTY_VALUE 参数为 1，该信号置位表示 IO_FIFO 剩余 1 个数可读
  • 配置 ALMOST_EMPTY_VALUE 参数为 2，该信号置位表示 IO_FIFO 剩余 2 个数可读
• ALMOST FULL：
  • 配置 ALMOST_FULL_VALUE 参数为 1，该信号置位表示 IO_FIFO 剩余 1 个数可写
  • 配置 ALMOST_FULL_VALUE 参数为 2，该信号置位表示 IO_FIFO 剩余 2 个数可写

参考资料

• ug953-Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide

• ug912-Vivado Design Suite Properties Reference Guide

• ug471-7 Series FPGAs SelectIO Resources User Guide

• ds181-Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics

• ds182-Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

• xapp523-LVDS 4x Asynchronous Oversampling Using 7 Series FPGAs Application Note

• xapp1017-LVDS Source Synchronous DDR Deserialization (up to 1,600 Mb/s) Application Note

• xapp524-Serial LVDS High-Speed ADC Interface Application Note