n位串行进位全加器

// 一位半加器

module h_adder(
 input        A,		// 被加数
 input        B,		// 加数
 output       S,		// 和数
 output       CO		// 进位
 );
 
 assign CO = A & B;
 assign S = A ^ B;
 
 endmodule

// 一位全加器

module f_adder(
	ain,
	bin,
	cin,
	cout,
	sum
);


input 	wire 		ain;
input 	wire	    bin;
input 	wire	    cin;
output 	wire		cout;
output 	wire		sum;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;

h_adder	b2v_inst(
	.A(ain),
	.B(bin),
	.CO(SYNTHESIZED_WIRE_0),
	.S(SYNTHESIZED_WIRE_2));

h_adder	b2v_inst2(
	.A(SYNTHESIZED_WIRE_2),
	.B(cin),
	.CO(SYNTHESIZED_WIRE_1),
	.S(sum));
	
assign  cout = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1;


endmodule

`timescale 1ns/1ns

module f_adder_n	#(	parameter 	n = 16)(
	input					[n-1:0]		ain,		// 被加数
	input					[n-1:0]		bin,		// 加数
	input								cin,		// 进位输入
	
	output								cout,		// 进位输出
	output					[n-1:0]		sum		// 和数输出
	);

	
	wire    				[n-1:0] 		c;
				
	genvar	i;
	generate
		for(i = 0; i < n; i = i+1) begin: adder_inst
			if(i == 0) begin
				f_adder u_f_adder(
					 .ain(ain[i]),
					 .bin(bin[i]),
					 .cin(cin),
					 .cout(c[i]),
					 .sum(sum[i])
					 );
			end
			else if(i == (n-1)) begin
				f_adder u_f_adder(
					 .ain(ain[i]),
					 .bin(bin[i]),
					 .cin(c[i-1]),
					 .cout(cout),
					 .sum(sum[i])
					 );
			end
			else begin
				f_adder u_f_adder(
					 .ain(ain[i]),
					 .bin(bin[i]),
					 .cin(c[i-1]),
					 .cout(c[i]),
					 .sum(sum[i])
					 );
			end
		end
	endgenerate
	
endmodule

testbench文件

`timescale 1ns/1ns

`define clk_period 10

module f_adder_n_tb;

	parameter    		n = 16;
	
	reg					clk;
	
	reg	[n-1:0]			ain;
	reg	[n-1:0]			bin;
	
	reg					cin;
	wire				cout;
	
	wire	[n-1:0]		sum;
	
	f_adder_n u1(
		.ain			(ain),
		.bin			(bin),
		.cin			(cin),
		.cout			(cout),
		.sum			(sum)
		);
	
	initial begin
		ain = 16'hf0aa;
		bin = 16'haa03;
		cin = 1'b1;
		
		#20;
		ain = 16'hf13a;
		bin = 16'ha223;
		cin = 1'b0;
	end
	
	always begin
		#10 clk = ~clk;
	end
endmodule

仿真截图