异步寄存器仿真

程序：

module jicunqi(
input clk,
input n_rst,
input load,
input [1:0]D,
output  [1:0]Q 
 );
 reg [1:0]Q;
  always @ (posedge clk or negedge n_rst)
    if (!n_rst)
    Q <= 0;
    else 
    if (load)
        Q <= D;
endmodule

testbench：

module jicunqi_test();
reg clk;
reg n_rst;
reg load;
reg [1:0]D;
wire [1:0]Q; 

initial begin
clk = 0 ; //初始值为0
n_rst = 0;
D = 2'b0;
load = 0;

#20
D <= 2'd2;

#40 
n_rst <= 1;
load <= 1;

#40
load <= 0;

#20
load <= 1;
D <= 2'b1;

#60
n_rst <= 0;
end

always #10 begin clk = ~clk ; end //20一个周期

jicunqi tb(
.clk(clk),
.n_rst(n_rst),
.load(load),
.D(D),
.Q(Q) 
);

endmodule

仿真图：