牛客网Verilog刷题——VL35

题目

  设计一个状态机，用来检测序列 10111，要求：
（1）进行非重叠检测 即101110111 只会被检测通过一次；
（2）寄存器输出且同步输出结果；
  注意rst为低电平复位，信号示意图如下。

  波形示意图：

  输入输出描述：

信号	类型	输入/输出	位宽	描述
clk	wire	Intput	1	系统时钟信号
rst_n	wire	Intput	1	异步复位信号，低电平有效
data	wire	Intput	1	单比特串行输入数据
flag	reg	Output	1	检测通过信号

答案

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
reg [4:0] curr_state;
reg [4:0] next_state;

localparam S0 = 5'b00001,
           S1 = 5'b00010,
           S2 = 5'b00100,
           S3 = 5'b01000,
           S4 = 5'b10000;

always @(posedge clk or negedge rst)
  if(!rst)
    curr_state <= S0;
  else
    curr_state <= next_state;

always @(*)
  case(curr_state)
    S0: next_state = data ? S1 : S0; //1
    S1: next_state = data ? S1 : S2; //0
    S2: next_state = data ? S3 : S0; //1
    S3: next_state = data ? S4 : S2; //1
    S4: next_state = data ? S0 : S2; //1
    default: next_state = S0;
  endcase

always @(posedge clk or negedge rst)
  if(!rst)
    flag <= 1'b0;
  else if(curr_state == S4 && data)
    flag <= 1'b1;
  else
    flag <= 1'b0;

//*************code***********//
endmodule