Mentor-dft 学习笔记 day2--overview部分(ATPG，fault models)

ps：工欲善其事，必先利其器

#仅仅是overview，不要关注细节，细节的部分我后面会写

一.Test Structure Insertion with Tessent Scan

Mentor Graphics 内部扫描和工具将顺序单元链接成扫描链

具体支持

• Verilog format

Reads and writes a Verilog gate-level netlist.

#读写verilog的门级网表

• Multiple scan types

Supports insertion of three different scan types, or methodologies: mux-DFF, clocked

scan, and LSSD.

#三种扫描类型

• Multiple test structures

Supports identification and insertion of scan (both sequential ATPG-based and scan

sequential procedure-based), wrapper chains, and test points.

#支持的测试结构

• Scannability checking

Provides powerful scannability checking/reporting capabilities for sequential elements

in the design.

#检查是否可扫描

• Design rules checking

Performs design rules checking to ensure scan setup and operation are correct—before

scan is actually inserted. This rules checking also guarantees that the scan insertion done

by Tessent Scan produces results that function properly in an ATPG tool.

#众嗦粥汁 drc

• Interface to ATPG tools

Automatically generates information for the ATPG tools on how to operate the scan

circuitry Tessent Scan creates.

#atpg接口

• Optimal partial scan selection

Provides optimal partial scan analysis and insertion capabilities.

• Flexible scan configurations

Allows flexibility in the scan stitching process, such as stitching scan cells in fixed or

random order, creating either single- or multiple-scan chains, and using multiple clocks

on a single-scan chain.

• Test logic

Provides capabilities for inserting test logic circuitry on uncontrollable set, reset, clock,

tri-state enable, and RAM read/write control lines.

• User specified pins

Allows user-specified pin names for test and other I/O pins.

• Multiple model levels

Handles gate-level, as well as gate/transistor-level models.

 ps：完善的功能让mentor在三大家的地位不可撼动（震撼脸）

二.  ATPG Overview

# 这里还是先来一段英文的介绍（

ATPG stands for Automatic Test Pattern Generation. Test patterns, sometimes called test

vectors, are sets of 1s and 0s placed on primary input pins during the manufacturing test process

to determine if the chip is functioning properly）

#其实最关键的还是我标红的信号，属于激励信号加持，用自定义的01信号代替主引脚的输入信号，再通过ate进行比对