SV Testbench 案例学习与思考-1

最新推荐文章于 2023-08-06 01:53:48 发布
最新推荐文章于 2023-08-06 01:53:48 发布
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分类专栏： SystemVerilog & Questa Sim 文章标签： 学习 systemverilog testbench
From Xu_Y_B
本文链接：https://blog.csdn.net/qq_43045275/article/details/129961943
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引言

关于Systemverilog语法学习的专栏博客已经告一段落，现在结合 chipverify 官网给出的几个testbench 案例，利用 QuestaSim 平台实做一些练习。

设计

// ---- ---- Design module
// 简述：数据地址选通
module switch #(
parameter ADDR_WIDTH 	= 		8,
parameter DATA_WIDTH 	= 		16,
parameter ADDR_DIV   	= 		8'h3f 
)(
input 							clk,
input 							rstn,
input 							vld,
input [ADDR_WIDTH-1:0] 			addr,
input [DATA_WIDTH-1:0] 			data,

output reg [ADDR_WIDTH-1:0] 	addr_a,
output reg [DATA_WIDTH-1:0] 	data_a,

output reg [ADDR_WIDTH-1:0] 	addr_b,
output reg [DATA_WIDTH-1:0] 	data_b
);

always@(posedge clk)
begin
	if(~rstn)
	begin
		addr_a <= 0;
		data_a <= 0;
		addr_b <= 0;
		data_b <= 0;
	end
	else
	begin
		if(vld)
		begin
			if(addr >=0 & addr <= ADDR_DIV)
			begin
				addr_a <= addr;
				data_a <= data;
				addr_b <= 0;
				data_b <= 0;				
			end
			else
			begin
				addr_a <= 0;
				data_a <= 0;
				addr_b <= addr;
				data_b <= data;					
			end
		end
	end
end
endmodule

这个案例的设计模块其实逻辑很简单，就是一个地址数据选择赋值功能，当地址在前半区间时，将地址和数据一并赋值给 a 通道；否则赋值给 b 通道。

事务对象

// ---- ---- Transaction Object
// 简述：事务对象
class switch_item;
	rand bit [7:0]  addr;		
	rand bit [15:0] data;		
	     bit [7:0]  addr_a;		
	     bit [15:0] data_a;		
	     bit [7:0]  addr_b;		
	     bit [15:0] data_b;		

	function void print(string tag="");
		$display("T = %0t %s addr = 0x%0h data = 0x%0h addr_a = 0x%0h data_a = 0x%0h addr_b = 0x%0h data_b = 0x%0h",
				  $time,tag,addr,data,addr_a,data_a,addr_b,data_b);
	endfunction
endclass

事务对象基本作为对象给驱动器提供被驱动事务，输入（激励）信号一般用 rand 关键字声明，因为在每次激励时产生随机数进行测试验证。输出（响应信号） 则不必用 rand 关键字。

数据生成器

// ---- ---- Generator
// 简述：测试数据生成
class generator;
	mailbox drv_mbx;
	event drv_done;
	int num = 20;

	task run();
		for(int i = 0; i < num; i++)
		begin
			switch_item item = new;
			item.randomize();
			$display("T = %0t [Generator] Loop : %0d/%0d creat next item",$time,i+1,num);
			drv_mbx.put(item);
			@(drv_done);
		end
		$display("T = %0t [Generator] Done generation of %0d items",$time,num);
	endtask
endclass

此部分代码主要是实现了一个数据生成器的类，类内的任务 run 每次创建一个新的事务对象，产生随即激励数据，通过 mailbox 传入驱动器。

接口

// ---- ---- Interface
interface switch_if (input bit clk);
	logic 			rstn;
	logic 			vld;
	logic [7:0] 	addr;
	logic [15:0] 	data;
	logic [7:0] 	addr_a;
	logic [15:0] 	data_a;
	logic [7:0] 	addr_b;
	logic [15:0] 	data_b;
endinterface

此处接口定义的地方也可以用 virtual 关键字，声明为虚接口； 

驱动器

// ---- ---- Driver
// 简述：驱动器
class driver;
	virtual switch_if vif;//虚拟接口：每个接口实例是独立的，互不影响
	event drv_done;
	mailbox drv_mbx;

	task run();
		$display("T = %0t [Driver] starting ...",$time);
		@(posedge vif.clk);

		forever
		begin
			switch_item item;

			$display("T = %0t [Driver] waiting for item ...",$time);
			drv_mbx.get(item);
			item.print("Driver");
			vif.vld <= 1;
			vif.addr <= item.addr;
			vif.data <= item.data;

			@(posedge vif.clk);
			vif.vld <= 0; ->drv_done;
		end
	endtask
endclass

注意此处代码内对接口的实例化使用了 virtual 关键字；虚接口的实例彼此之间独立互不影响。

drv_mbx 通过 mailbox 获取事务对象，然后将 vld 有效信号拉高，地址和数据各自赋值。

最后将 vld 信号拉低 触发 drv_done 事件。

监视器

// ---- ---- Monitor
// 简述：
class monitor;
	virtual switch_if vif;
	mailbox scb_mbx;
	semaphore sema4;

	function new ();
		sema4 = new(1);
	endfunction 

	task run();
		$display("T = %0t [Monitor] starting ...",$time);

		fork
			sample_port("Thread0");
			sample_port("Thread1");
		join
	endtask

	task sample_port(string tag="");
		forever
		begin
			@(posedge vif.clk);
			if(vif.rstn & vif.vld)
			begin
				switch_item item = new;
				sema4.get();
				item.addr = vif.addr;
				item.data = vif.data;
				$display("T = %0t [Monitor] %s First part over",$time,tag);

				@(posedge vif.clk);
				sema4.put();
				item.addr_a = vif.addr_a;
				item.data_a = vif.data_a;
				item.addr_b = vif.addr_b;
				item.data_b = vif.data_b;
				$display("T = %0t [Monitor] %s Second part over",$time,tag);

				scb_mbx.put(item);
				item.print({"Monitor_",tag});
			end
		end
	endtask

endclass

监视器部分的代码涉及到两个线程对同一个内存区域的读写操作，为避免冲突，此处引入 semaphore 。

计分板

// ---- ---- Scoreboard
// 简介：
class scoreboard;
	mailbox scb_mbx;

	task run();
		forever
		begin
			switch_item item;
			scb_mbx.get(item);

			if(item.addr inside{[0:'h3f]})
			begin
				if(item.addr_a != item.addr | item.data_a != item.data)
					$display("T = %0t [Scoreboard] ERRROR! Mismatch addr=0x%0h data=0x%0h addr_a=0x%0h data_a=0x%0h",$time,item.addr ,item.data ,item.addr_a ,item.data_a);
				else
					$display("T = %0t [Scoreboard] PASS! Match addr=0x%0h data=0x%0h addr_a=0x%0h data_a=0x%0h",$time,item.addr ,item.data ,item.addr_a ,item.data_a);
			end
			else
			begin
				if(item.addr_b != item.addr | item.data_b != item.data)
					$display("T = %0t [Scoreboard] ERRROR! Mismatch addr=0x%0h data=0x%0h addr_b=0x%0h data_b=0x%0h",$time,item.addr ,item.data ,item.addr_b ,item.data_b);
				else
					$display("T = %0t [Scoreboard] PASS! Match addr=0x%0h data=0x%0h addr_b=0x%0h data_b=0x%0h",$time,item.addr ,item.data ,item.addr_b ,item.data_b);
			end
		end
	endtask
endclass

主要就是对设计的功能作判断，对比输入输出是否一致。给出判断信息。

环境

// ---- ---- Environment
// 简介：
class env;
	driver d0;
	monitor m0;
	generator g0;
	scoreboard s0;

	mailbox drv_mbx;
	mailbox scb_mbx;
	event drv_done;

	virtual switch_if vif;

	function new ();
		d0 = new;
		m0 = new;
		g0 = new;
		s0 = new;
		drv_mbx = new();
		scb_mbx = new();

		d0.drv_mbx = drv_mbx;
		g0.drv_mbx = drv_mbx;
		m0.scb_mbx = scb_mbx;
		s0.scb_mbx = scb_mbx;

		d0.drv_done = drv_done;
		g0.drv_done = drv_done;
	endfunction 

	virtual task run();
		d0.vif = vif;
		m0.vif = vif;

		fork
			d0.run();
			m0.run();
			g0.run();
			s0.run();
		join_any
	endtask
endclass

 环境主要负责构建 testbench 的基本对象、事件、任务等。

测试

// ---- ---- Test
class test;
	env e0;

	function new ();
		e0 = new;
	endfunction 

	task run();
		e0.run();
	endtask
endclass

测试可以看作是，执行环境中对应的任务。

测试顶层

// ---- ---- TB_TOP
module TB_TOP ();
reg clk;

always #10 clk=~clk;

switch_if _if(clk);

parameter ADDR_WIDTH 	= 		8;
parameter DATA_WIDTH 	= 		16;
parameter ADDR_DIV   	= 		8'h3f ;

	switch #(
			.ADDR_WIDTH(ADDR_WIDTH),
			.DATA_WIDTH(DATA_WIDTH),
			.ADDR_DIV(ADDR_DIV)
		) inst_switch (
			.clk    (clk),
			.rstn   (_if.rstn),
			.vld    (_if.vld),
			.addr   (_if.addr),
			.data   (_if.data),
			.addr_a (_if.addr_a),
			.data_a (_if.data_a),
			.addr_b (_if.addr_b),
			.data_b (_if.data_b)
		);


test t0;

initial
begin
	{clk,_if.rstn} <= 0;

	#20 _if.rstn <= 1;
	t0 = new;
	t0.e0.vif = _if;
	t0.run();

	#50 $finish;
end

endmodule

顶层需要例化设计文件，给时钟激励，执行测试。

为方便编译，建议将上述所有代码放在一个 sv 文件中。

QuestaSim 给出的仿真结果：

# T = 20 [Driver] starting ...
# T = 20 [Monitor] starting ...
# T = 20 [Generator] Loop : 1/20 creat next item
# T = 30 [Driver] waiting for item ...
# T = 30 Driver addr = 0xfb data = 0x78ad addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 50 [Driver] waiting for item ...
# T = 50 [Monitor] Thread0 First part over
# T = 50 [Generator] Loop : 2/20 creat next item
# T = 50 Driver addr = 0xce data = 0x6676 addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 70 [Driver] waiting for item ...
# T = 70 [Monitor] Thread0 Second part over
# T = 70 Monitor_Thread0 addr = 0xfb data = 0x78ad addr_a = 0x0 data_a = 0x0 addr_b = 0xfb data_b = 0x78ad
# T = 70 [Generator] Loop : 3/20 creat next item
# T = 70 [Monitor] Thread1 First part over
# T = 70 [Scoreboard] PASS! Match addr=0xfb data=0x78ad addr_b=0xfb data_b=0x78ad
# T = 70 Driver addr = 0xc0 data = 0x69be addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 90 [Driver] waiting for item ...
# T = 90 [Monitor] Thread1 Second part over
# T = 90 Monitor_Thread1 addr = 0xce data = 0x6676 addr_a = 0x0 data_a = 0x0 addr_b = 0xce data_b = 0x6676
# T = 90 [Monitor] Thread0 First part over
# T = 90 [Generator] Loop : 4/20 creat next item
# T = 90 [Scoreboard] PASS! Match addr=0xce data=0x6676 addr_b=0xce data_b=0x6676
# T = 90 Driver addr = 0x36 data = 0x317 addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 110 [Driver] waiting for item ...
# T = 110 [Monitor] Thread0 Second part over
# T = 110 Monitor_Thread0 addr = 0xc0 data = 0x69be addr_a = 0x0 data_a = 0x0 addr_b = 0xc0 data_b = 0x69be
# T = 110 [Monitor] Thread1 First part over
# T = 110 [Generator] Loop : 5/20 creat next item
# T = 110 [Scoreboard] PASS! Match addr=0xc0 data=0x69be addr_b=0xc0 data_b=0x69be
# T = 110 Driver addr = 0x71 data = 0x16ba addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 130 [Driver] waiting for item ...
# T = 130 [Monitor] Thread1 Second part over
# T = 130 Monitor_Thread1 addr = 0x36 data = 0x317 addr_a = 0x36 data_a = 0x317 addr_b = 0x0 data_b = 0x0
# T = 130 [Monitor] Thread0 First part over
# T = 130 [Generator] Loop : 6/20 creat next item
# T = 130 [Scoreboard] PASS! Match addr=0x36 data=0x317 addr_a=0x36 data_a=0x317
# T = 130 Driver addr = 0x6e data = 0x23f4 addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 150 [Driver] waiting for item ...
# T = 150 [Monitor] Thread0 Second part over
# T = 150 Monitor_Thread0 addr = 0x71 data = 0x16ba addr_a = 0x0 data_a = 0x0 addr_b = 0x71 data_b = 0x16ba
# T = 150 [Monitor] Thread1 First part over
# T = 150 [Generator] Loop : 7/20 creat next item
# T = 150 [Scoreboard] PASS! Match addr=0x71 data=0x16ba addr_b=0x71 data_b=0x16ba
# T = 150 Driver addr = 0x47 data = 0x4fb2 addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 170 [Driver] waiting for item ...
# T = 170 [Monitor] Thread1 Second part over
# T = 170 Monitor_Thread1 addr = 0x6e data = 0x23f4 addr_a = 0x0 data_a = 0x0 addr_b = 0x6e data_b = 0x23f4
# T = 170 [Monitor] Thread0 First part over
# T = 170 [Generator] Loop : 8/20 creat next item
# T = 170 [Scoreboard] PASS! Match addr=0x6e data=0x23f4 addr_b=0x6e data_b=0x23f4
# T = 170 Driver addr = 0xbb data = 0xcd69 addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 190 [Driver] waiting for item ...
# T = 190 [Monitor] Thread0 Second part over
# T = 190 Monitor_Thread0 addr = 0x47 data = 0x4fb2 addr_a = 0x0 data_a = 0x0 addr_b = 0x47 data_b = 0x4fb2
# T = 190 [Monitor] Thread1 First part over
# T = 190 [Generator] Loop : 9/20 creat next item
# T = 190 [Scoreboard] PASS! Match addr=0x47 data=0x4fb2 addr_b=0x47 data_b=0x4fb2
# T = 190 Driver addr = 0x35 data = 0x9e58 addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 210 [Driver] waiting for item ...
# T = 210 [Monitor] Thread1 Second part over
# T = 210 Monitor_Thread1 addr = 0xbb data = 0xcd69 addr_a = 0x0 data_a = 0x0 addr_b = 0xbb data_b = 0xcd69
# T = 210 [Monitor] Thread0 First part over
# T = 210 [Generator] Loop : 10/20 creat next item
# T = 210 [Scoreboard] PASS! Match addr=0xbb data=0xcd69 addr_b=0xbb data_b=0xcd69
# T = 210 Driver addr = 0x49 data = 0xd196 addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 230 [Driver] waiting for item ...
# T = 230 [Monitor] Thread0 Second part over
# T = 230 Monitor_Thread0 addr = 0x35 data = 0x9e58 addr_a = 0x35 data_a = 0x9e58 addr_b = 0x0 data_b = 0x0
# T = 230 [Monitor] Thread1 First part over
# T = 230 [Generator] Loop : 11/20 creat next item
# T = 230 [Scoreboard] PASS! Match addr=0x35 data=0x9e58 addr_a=0x35 data_a=0x9e58
# T = 230 Driver addr = 0xca data = 0x1207 addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 250 [Driver] waiting for item ...
# T = 250 [Monitor] Thread1 Second part over
# T = 250 Monitor_Thread1 addr = 0x49 data = 0xd196 addr_a = 0x0 data_a = 0x0 addr_b = 0x49 data_b = 0xd196
# T = 250 [Monitor] Thread0 First part over
# T = 250 [Generator] Loop : 12/20 creat next item
# T = 250 [Scoreboard] PASS! Match addr=0x49 data=0xd196 addr_b=0x49 data_b=0xd196
# T = 250 Driver addr = 0x5b data = 0x1d5b addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 270 [Driver] waiting for item ...
# T = 270 [Monitor] Thread0 Second part over
# T = 270 Monitor_Thread0 addr = 0xca data = 0x1207 addr_a = 0x0 data_a = 0x0 addr_b = 0xca data_b = 0x1207
# T = 270 [Monitor] Thread1 First part over
# T = 270 [Generator] Loop : 13/20 creat next item
# T = 270 [Scoreboard] PASS! Match addr=0xca data=0x1207 addr_b=0xca data_b=0x1207
# T = 270 Driver addr = 0xbc data = 0x2688 addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 290 [Driver] waiting for item ...
# T = 290 [Monitor] Thread1 Second part over
# T = 290 Monitor_Thread1 addr = 0x5b data = 0x1d5b addr_a = 0x0 data_a = 0x0 addr_b = 0x5b data_b = 0x1d5b
# T = 290 [Monitor] Thread0 First part over
# T = 290 [Generator] Loop : 14/20 creat next item
# T = 290 [Scoreboard] PASS! Match addr=0x5b data=0x1d5b addr_b=0x5b data_b=0x1d5b
# T = 290 Driver addr = 0x97 data = 0x559d addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 310 [Driver] waiting for item ...
# T = 310 [Monitor] Thread0 Second part over
# T = 310 Monitor_Thread0 addr = 0xbc data = 0x2688 addr_a = 0x0 data_a = 0x0 addr_b = 0xbc data_b = 0x2688
# T = 310 [Monitor] Thread1 First part over
# T = 310 [Generator] Loop : 15/20 creat next item
# T = 310 [Scoreboard] PASS! Match addr=0xbc data=0x2688 addr_b=0xbc data_b=0x2688
# T = 310 Driver addr = 0x3c data = 0xe700 addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 330 [Driver] waiting for item ...
# T = 330 [Monitor] Thread1 Second part over
# T = 330 Monitor_Thread1 addr = 0x97 data = 0x559d addr_a = 0x0 data_a = 0x0 addr_b = 0x97 data_b = 0x559d
# T = 330 [Monitor] Thread0 First part over
# T = 330 [Generator] Loop : 16/20 creat next item
# T = 330 [Scoreboard] PASS! Match addr=0x97 data=0x559d addr_b=0x97 data_b=0x559d
# T = 330 Driver addr = 0x79 data = 0x5f5f addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 350 [Driver] waiting for item ...
# T = 350 [Monitor] Thread0 Second part over
# T = 350 Monitor_Thread0 addr = 0x3c data = 0xe700 addr_a = 0x3c data_a = 0xe700 addr_b = 0x0 data_b = 0x0
# T = 350 [Monitor] Thread1 First part over
# T = 350 [Generator] Loop : 17/20 creat next item
# T = 350 [Scoreboard] PASS! Match addr=0x3c data=0xe700 addr_a=0x3c data_a=0xe700
# T = 350 Driver addr = 0x63 data = 0xd727 addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 370 [Driver] waiting for item ...
# T = 370 [Monitor] Thread1 Second part over
# T = 370 Monitor_Thread1 addr = 0x79 data = 0x5f5f addr_a = 0x0 data_a = 0x0 addr_b = 0x79 data_b = 0x5f5f
# T = 370 [Monitor] Thread0 First part over
# T = 370 [Generator] Loop : 18/20 creat next item
# T = 370 [Scoreboard] PASS! Match addr=0x79 data=0x5f5f addr_b=0x79 data_b=0x5f5f
# T = 370 Driver addr = 0x3 data = 0x770e addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 390 [Driver] waiting for item ...
# T = 390 [Monitor] Thread0 Second part over
# T = 390 Monitor_Thread0 addr = 0x63 data = 0xd727 addr_a = 0x0 data_a = 0x0 addr_b = 0x63 data_b = 0xd727
# T = 390 [Monitor] Thread1 First part over
# T = 390 [Generator] Loop : 19/20 creat next item
# T = 390 [Scoreboard] PASS! Match addr=0x63 data=0xd727 addr_b=0x63 data_b=0xd727
# T = 390 Driver addr = 0xab data = 0x489a addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 410 [Driver] waiting for item ...
# T = 410 [Monitor] Thread1 Second part over
# T = 410 Monitor_Thread1 addr = 0x3 data = 0x770e addr_a = 0x3 data_a = 0x770e addr_b = 0x0 data_b = 0x0
# T = 410 [Monitor] Thread0 First part over
# T = 410 [Generator] Loop : 20/20 creat next item
# T = 410 [Scoreboard] PASS! Match addr=0x3 data=0x770e addr_a=0x3 data_a=0x770e
# T = 410 Driver addr = 0x63 data = 0x2527 addr_a = 0x0 data_a = 0x0 addr_b = 0x0 data_b = 0x0
# T = 430 [Driver] waiting for item ...
# T = 430 [Monitor] Thread0 Second part over
# T = 430 Monitor_Thread0 addr = 0xab data = 0x489a addr_a = 0x0 data_a = 0x0 addr_b = 0xab data_b = 0x489a
# T = 430 [Monitor] Thread1 First part over
# T = 430 [Generator] Done generation of 20 items
# T = 430 [Scoreboard] PASS! Match addr=0xab data=0x489a addr_b=0xab data_b=0x489a
# T = 450 [Monitor] Thread1 Second part over
# T = 450 Monitor_Thread1 addr = 0x63 data = 0x2527 addr_a = 0x0 data_a = 0x0 addr_b = 0x63 data_b = 0x2527
# T = 450 [Scoreboard] PASS! Match addr=0x63 data=0x2527 addr_b=0x63 data_b=0x2527

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硬件描述语言（Hardware Description Language， HDL）是用于描述硬件行为的语言，可以在寄存器传输级、行为级、逻辑门级等对数字电路系统进行描述。为了验证HDL中的硬件描述是否正确，我们需要搭建一个testbench，来验证RTL代码是否正确无误。因此诞生这种具有更多功能的验证语言SystemVerilog。 SystemVerilog是Verilog的扩展，可以完全兼容Verilog。它具有面向对象的特性，同时还具有随机化、约束和功能覆盖率等特性。提供了DPI接口，可以把C/C+
SystemVerilog Testbench Lab4: oop encapsulatio
JJJJJJJerry的博客
08-16 553
OOP encapsulation意为面向对象封装。Lab4做的事情就是将packet信息——sa、da和payload封装成一个Packet类，在generator中创建随机的Packet对象。 Packet class 在我看到的很多sv文件中，都会使用宏定义来防止多次编译。 `ifndef INC_PACKET_SV `define INC_PAKET_SV class Packet; rand bit[3:0] sa, da; rand logic[7:0] payload[$]; strin
testbench简单范例
zhuoxiaohao的专栏
06-25 6166
最简单的一个testbench
systemverilog验证测试平台编写指南_Testbench编写指南（1）基本组成与示例
weixin_39945915的博客
12-16 796
对于小型设计来说，最好的测试方式便是使用TestBench和HDL仿真器来验证其正确性。一般TestBench需要包含这些部分：实例化待测试设计、使用测试向量激励设计、将结果输出到终端或波形窗口便于可视化观察、比较实际结果和预期结果。下面是一个标准的HDL验证流程： TestBench可以用VHDL或Verilog、SystemVerilog编写，本文以Verilog HDL为例。FPGA设计必须...
SV实验1 基于SV的Testbench
PoPo's Blog
02-26 1883
SV实验1和2部分的学习记录，Testbench逐渐由硬件环境转变为软件环境。
SV的testbench例子-加法器
bleauchat的博客
05-26 4642
下图是一个加法器的框图： 输入管脚包括a、b、valid和clk、reset，以及一个输出管脚c。 TestBench Without Monitor, Agent and Scoreboard 不带monitor、agent和scoreboard的结构如下： （1）定义transaction transaction的作用主要是定义随机化的输入输出管脚，并输出显示. ...
SV之testbench概述
bleauchat的博客
05-25 1895
What is the purpose of a testbench ? testbench允许我们通过仿真来验证设计的功能，它包括了设计以及驱动设计的激励. （1）产生不同类型的输入激励； （2）利用产生的激励驱动设计； （3）设计处理输入产生输出； （4）对比设计的输出与期望的输出； （5）如果发现功能bug则修改设计以修复bug； Components of a testben...
TestBench内容编写与方法总结
jk_101的博客
03-27 510
1、不要设置无意义的高精度，时间精度越高，对应的仿真所消耗的资源和时间就越多，比如“`timescale 1ns/1ps”，一般仿真时不需要精确到ps级，所以只需要设置成ns级就行，比如“`timescale 1ns/1ns”。表示打印的时间值的单位， 0 表示秒，-3 表示毫秒，-6 表示微秒，-9 表示纳秒， -12 表示皮秒， -15 表示飞秒；-10表示以100ps为单位。$stop表示暂停仿真，当程序仿真执行到该语句时，仿真会暂停，常用于抓取仿真过程中出现错误状态时，或检测某个信号时，暂停仿真。
SV语言部分（2）
2301_76431006的博客
04-20 534
关于接口，以及与接口相关的一些知识点，大家快来学习吧！！！
SV 第四章 连接设计和测试平台
最新发布
Minx
08-06 212
验证需要几个步骤，生成输入激励，捕获输出响应，决定对错和衡量进度。首先需要将一个合适的测试平台连接到设计上。测试平台包裹着设计（DUT，Design Under Test），发送激励并捕获设计的输出。
SystemVerilogTestbenchLabGuide教材.pdf
04-18
snps system verilog workshop 官方培训文档，适用于芯片设计及验证工程师，经典教材，不容错过
编了个计数器程序与TESTBENCH
12-09
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity counters is port( reset : in std_logic; cs : in std_logic; clk : in std_logic;...
AXIS-interconnect-testbench.zip
01-13
xilinx AXI4-Stream-interconnect 仿真testbench文件，包含 AXI4-Stream traffic generator文件，自定义随机帧长，随机报文等，仅供学习参考。
Modsim-AND-testbench.zip_TESTBENCH_modsim
09-23
关于fpga中，测试平台testbench的技巧，及仿真软件MOSIDISIM
simpel_ADDER_with_sv_testbench-
03-07
simpel_ADDER_with_sv_testbench-
apache-bench-dotnet-core-load-test:中篇文章样本申请
05-08
如何使用Apache Bench加载Asp.Net Core Web Api服务（ab） 中等文章中提到的示例应用程序。
【SystemVerilog项目实践】7.AHB-SRAMC（编写Systemverilog Testbench-3）
托马斯的博客
07-25 2454
编写Systemverilog Testbench-3
原子测试在svtb(systemverilog testbench)中的应用
XtremeDV
06-04 954
首先引入原子测试的概念：原子测试是一种专注于测试单一功能的测试，它明确了解您测试的是什么。如果测试失败，那么您还应该清楚需要修复的问题。例如，比较两个数组是相等，通常我们会首先判断数组大小是否一致，然后比较每个元素是否相等，如果大小一致，且每个元素都相等，那么我们认为这两个数组相等。那么有没有更简洁的写法呢？如果告诉你其实可以直接将两个数组进行比较，你该怎么测试这个语法是否正确呢？if(array...
sv testbench workship lab guide 是什么意思
06-02
"sv testbench workship lab guide" 可能是一个关于 SystemVerilog（SV）测试台架（testbench）工作坊（workshop）的实验指南（lab guide）。其中，SV是一种硬件描述语言（HDL），用于设计和验证数字电路。测试台架是用于检查设计是否符合规范和功能是否正确的工具。工作坊则是一个集中讨论和实践某一主题的培训课程。实验指南则提供了关于实验流程、步骤和要求的详细说明。

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