verilog 练习一：八位数据比较器 modelsim

//8位数据比较器
//若a[7:0]大于b[7:0]，则输出高电平，否则输出低电平

module comp_8(a,b,great); 
input  [7:0] a,b;
output great;
reg    great;

always @(a or b)
       if ( a > b )
	       great = 1;
	   else
	       great = 0;
		   
endmodule

测试文件

`timescale 1ns/1ns
module comp_8_tb();
reg [7:0] a;
reg [7:0] b;
wire great;

initial
   begin
        a = 8'b0000_0000;
		b = 8'b0000_0000;
		#100 a = 8'b0000_0000; b = 8'b0000_0001;
		#100 a = 8'b0000_0001; b = 8'b0000_0001;
		#100 a = 8'b0000_0001; b = 8'b0000_0000;
		#100 a = 8'b0000_0000; b = 8'b0000_0000;
		#100 $stop;
	end	

comp_8 u1(
          .a(a),
		  .b(b),
		  .great(great)
		  );

endmodule

仿真结果