一、计数器
verilog代码:
//2023/3/28 lzp
//计数器
`timescale 1ns/10ps
module counter(clk, reset, y);
input clk, reset;
output[7:0] y;
reg[7:0] y; //触发器定义成reg型变量
wire[7:0] sum; //assign赋值,wire型变量
assign sum=y+1;
always@(posedge clk or negedge reset)
if(~reset) begin
y<=0; //reset为低电平时y寄存器复位
end
else begin
y<=sum;
end
endmodule
//计数器testbench
module counter_tb;
//参数定义
`define CLK_PERIORD 10 //时钟周期设置为10ns(100MHz)
reg clk, reset;
wire[7:0] y;
counter counter(.clk(clk), .reset(reset), .y(y));
//时钟和复位初始化、复位产生
initial begin
clk<=0;
reset<=0;
#100;
reset<=1;
#100;
$stop;
end
//时钟产生
always #(`CLK_PERIORD/2) clk = ~clk;
//测试激励产生
//initial begin
//end
endmodule
波形:
二、伪随机码发生器
代码:
//2023/3/28 lzp
//伪随机数发生器
`timescale 1ns/10ps
module random(clk, reset, y);
input clk, reset;
output y;
reg[3:0] d;
assign y=d[0];
always@(posedge clk or negedge reset)
if(~reset) begin
d<=4'b1111; //reset为低电平时y寄存器复位
end
else begin
d[2:0]<=d[3:1];
d[3]<=d[3]+d[0];
end
endmodule
//计数器testbench
module random_tb;
//参数定义
`define CLK_PERIORD 10 //时钟周期设置为10ns(100MHz)
reg clk, reset;
wire y;
random random(.clk(clk), .reset(reset), .y(y));
//时钟和复位初始化、复位产生
initial begin
clk<=0;
reset<=0;
#100;
reset<=1;
#1000;
$stop;
end
//时钟产生
always #(`CLK_PERIORD/2) clk = ~clk;
//测试激励产生
//initial begin
//end
endmodule