HDLBits_Lemmings3

最新推荐文章于 2024-09-09 14:48:28 发布

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最新推荐文章于 2024-09-09 14:48:28 发布

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文章标签： fpga开发

本文链接：https://blog.csdn.net/qq_55536224/article/details/137466570

版权

这篇文章详细描述了一个使用Verilog硬件描述语言编写的模块，通过状态机控制电路行为，根据地面、输入信号和挖掘操作决定行走、叫声和挖掘动作。

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module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
	
    reg [3:0] reg_out;
    reg [3:0] state,next_state;
    parameter[2:0]	s0=3'b000,//left_ground_nodig
    				s1=3'b001,//left_ground_dig
    				s2=3'b011,//left_unground_nodig
    				s3=3'b111,//right_ground_nodig
    				s4=3'b110,//right_ground_dig
    				s5=3'b100;//right_unground_nodig
    
    always @(*) begin
        case(state) 
            s0:begin
                if(ground) begin
                    if(dig ) 
                        next_state = s1;
                    else if((!dig) & bump_left)
                        next_state = s3;
                    else
                        next_state = s0;
                end
                else
                    next_state = s2;
            end
            
            s1:begin
                if(ground) begin
                    next_state = s1;
                end
                else
                    next_state = s2;
            end
            
            s2:begin
                if(ground)
                    next_state = s0;
                else
                    next_state = s2;
            end
            
            s3:begin
                if(ground) begin
                    if(dig ) 
                        next_state = s4;
                    else if ((!dig) & bump_right)
                        next_state = s0;
                    else
                        next_state = s3;
                end
                else
                    next_state = s5;
            end
            
            s4:begin
                if(ground)
                    next_state = s4;
                else 
                    next_state = s5;
            end
            
            s5:begin
                if(ground)
                    next_state = s3;
                else
                    next_state = s5;
            end
        endcase
    end
    
    always @(posedge clk or posedge areset) begin
        if(areset)
            state <= s0;
        else
            state <= next_state;
    end
    
    always @(*) begin 
        case(state)
            s0:reg_out = 4'b1000;
            s1:reg_out = 4'b0001;
            s2:reg_out = 4'b0010;
            s3:reg_out = 4'b0100;
            s4:reg_out = 4'b0001;
            s5:reg_out = 4'b0010;
        endcase
    end
    
    assign {walk_left,walk_right,aaah,digging} = reg_out;
endmodule