HDLBits_Fsm ps2data

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //
	
    reg [23:0] out_reg_temp,out_reg;
    reg [1:0] state,next_state;
    reg done_reg;
    parameter 	s0=2'b00,
    			s1=2'b01,
    			s2=2'b11,
    			s3=2'b10;
	
    always @(*) begin
        case(state)
            s0:begin 
                next_state = in[3]?s1:s0;
                out_reg_temp[23:16] = in[3]?in:8'b00000000; 
            end
            s1:begin
               	next_state = s2; 
                out_reg_temp[15:8] = in;
            end
            s2:begin
                next_state = s3;
                out_reg_temp[7:0] = in;
            end
            s3:begin
                next_state = in[3]?s1:s0;
                if(in[3])begin
                    out_reg_temp[23:16] = in;
                    out_reg_temp[15:0] = 0;
                end
                else
                    out_reg_temp = 0;
            end
        endcase
    end

    always @(posedge clk) begin
        if(reset) begin
            out_reg<=0;
            state<=s0;
        end
        else begin
           	out_reg<=out_reg_temp;
            state<=next_state;
        end
    end
    
    always @(*) begin
        done_reg = (state==s3);
    end
    
    assign done = done_reg;
    assign out_bytes = out_reg;
endmodule