代码截图:
代码:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity zy7 is
port(a,b:in std_logic_vector(3 downto 0);
y,y1,y2:out std_logic);
end entity zy7;
architecture jgt of zy7 is
begin
process(a,b)
begin
if(a>b) then
y<='1';y1<='0';y2<='0';
elsif(a=b) then
y<='0';y1<='1';y2<='0';
else
y<='0';y1<='0';y2<='1';
end if;
end process;
end architecture jgt;
测试代码:
library ieee;
use ieee.std_logic_1164.all;
entity zy7_t is
end entity zy7_t;
architecture jgt_t of zy7_t is
component zy7 is
port(a,b:in std_logic_vector(3 downto 0);
y,y1,y2:out std_logic);
end component zy7;
signal a,b:std_logic_vector(3 downto 0);
begin
instant:zy7 port map
(
a=>a,b=>b
);
process is
begin
a<="0000";
wait for 20 ns;
b<="0000";
wait for 20 ns;
a<="0001";
wait for 20 ns;
b<="0001";
wait for 20 ns;
a<="0010";
wait for 20 ns;
b<="0010";
wait for 20 ns;
a<="0011";
wait for 20 ns;
b<="0011";
wait for 20 ns;
a<="0100";
wait for 20 ns;
b<="0100";
wait for 20 ns;
a<="0101";
wait for 20 ns;
b<="0101";
wait for 20 ns;
a<="0110";
wait for 20 ns;
a<="0110";
wait for 20 ns;
b<="0111";
wait for 20 ns;
a<="0111";
wait for 20 ns;
b<="1000";
wait for 20 ns;
a<="1000";
wait for 20 ns;
b<="1001";
wait for 20 ns;
a<="1010";
wait for 20 ns;
b<="1010";
wait for 20 ns;
a<="1011";
wait for 20 ns;
b<="1011";
wait for 20 ns;
a<="1100";
wait for 20 ns;
b<="1100";
wait for 20 ns;
a<="1101";
wait for 20 ns;
b<="1101";
wait for 20 ns;
a<="1110";
wait for 20 ns;
b<="1110";
wait for 20 ns;
a<="1111";
wait for 20 ns;
b<="1111";
wait for 20 ns;
end process;
end architecture jgt_t;
仿真截图: