VHDL设计——交通红绿灯控制器模块

设计一个交通红绿灯控制器模块，实现主干道和支路之间红绿黄灯的信号转换。


Design Block:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TRAFFIC IS
	PORT(CLK,RST:IN STD_LOGIC;
		NSLIGHTS,WELIGHTS:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END TRAFFIC;
ARCHITECTURE BEHAV OF TRAFFIC IS
TYPE STATES IS (S0,S1,S2,S3);
	ATTRIBUTE ENUM_ENCODING:STRING;
	ATTRIBUTE ENUM_ENCODING OF STATES:TYPE IS "one-hot/gray";
	SIGNAL C_ST,N_ST:STATES:=S0;
	SIGNAL TIME0:STD_LOGIC_VECTOR(6 DOWNTO 0);
	BEGIN
	COUNT:PROCESS(CLK,RST)
	VARIABLE T:STD_LOGIC_VECTOR(6 DOWNTO 0);
		BEGIN
		IF RST='1' THEN T:=(OTHERS=>'0');
		ELSIF CLK'EVENT AND CLK='1' THEN 
			IF(T<68) THEN T:=T+1;
			ELSE T:=(OTHERS=>'0');
			END IF;
		END IF;
		TIME0<=T;
	END PROCESS COUNT;
	COM:PROCESS(C_ST,TIME0)
		BEGIN
		CASE C_ST IS
		WHEN S0 => NSLIGHTS<="010";WELIGHTS<="100";
			IF TIME0=39 THEN N_ST<=S1;
			ELSE N_ST<=S0;
			END IF;
		WHEN S1 => NSLIGHTS<="001";WELIGHTS<="100";
			IF TIME0=43 THEN N_ST<=S2;
			ELSE N_ST<=S1;
			END IF;
		WHEN S2 => NSLIGHTS<="100";WELIGHTS<="010";
			IF TIME0=63 THEN N_ST<=S3;
			ELSE N_ST<=S2;
			END IF;
		WHEN S3 => NSLIGHTS<="100";WELIGHTS<="001";
			IF TIME0=67 THEN N_ST<=S0;
			ELSE N_ST<=S3;
			END IF;
		END CASE;
	END PROCESS COM;
	REG:PROCESS(CLK,RST)
		BEGIN
		IF RST='1' THEN C_ST<=S0;
		ELSIF CLK'EVENT AND CLK='1' THEN C_ST<=N_ST;
		END IF;
	END PROCESS REG;
END BEHAV;

Test Bench:

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TRAFFIC_vhd_tst IS
END TRAFFIC_vhd_tst;
ARCHITECTURE TRAFFIC_arch OF TRAFFIC_vhd_tst IS                                                  
SIGNAL CLK1 : STD_LOGIC;
SIGNAL RST1 : STD_LOGIC;
SIGNAL NS : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL WE : STD_LOGIC_VECTOR(2 DOWNTO 0);
CONSTANT CLK_P:TIME:=1 us;
COMPONENT TRAFFIC
	PORT(CLK,RST:IN STD_LOGIC;
		NSLIGHTS,WELIGHTS:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT;
BEGIN
	i1 : TRAFFIC PORT MAP(CLK => CLK1, RST => RST1, NSLIGHTS => NS, WELIGHTS => WE);
	PROCESS
		BEGIN
		CLK1<='0'; WAIT FOR CLK_P;
		CLK1<='1'; WAIT FOR CLK_P;
	END PROCESS;
	RST1<='1','0' AFTER 2 us;
END TRAFFIC_arch;

仿真波形图：