相比于之前设计的状态机题目给出输入、要求我们自己写出状态变化、状态逻辑判断与输出,本题直接将现态本身作为输入,要求我们给出次态和输出。
搞清楚输入输出之后,鉴于独热码的特征,我们可以对输入/输出的每一位进行单独判断,其实如果从功能实现上出发也不是必须如此,只是题目中对输入有特殊说明。
The testbench will test with non-one hot inputs to make sure you’re not trying to do something more complicated.
也就是说,Testbench会给出非独热码的输入(比如10’b10_0001_0010)此时如果我们对输入作判断后,
- 直接将移位后的state赋值给next_state(如S1的state在“正常的”独热码情况下可以在输入为1时通过S0的state左移1位得到)
- 由于条件不满足直接跳转到default状态(S0)
均会导致错误的次态出现。所以应当对next_state的每一位单独判断,在输入in指定的情况下,根据输入现态的每一位确定是否会跳转到这个状态(也就是次态的这个位是否置1)。这样对于次态的每一位,都是由现态正确跳转而来,即使由于现态以非独热码的形式输入导致次态输出整体上并非独热码形式,但是对于单独的1位次态来说,结果都是正确的(每一位次态都认为其余次态的位均应为0,相当于把多个独热码叠加起来了)
给出Verilog HDL供大家参考:
module top_module(
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2);
assign next_state[0] = ~in & (state[0] | state[1] | state[2] |state[3] |state[4] | state[7] |state[8] |state[9]);
assign next_state[1] = in & (state[0] | state[8] | state[9]);
assign next_state[2] = in & state[1];
assign next_state[3] = in & state[2];
assign next_state[4] = in & state[3];
assign next_state[5] = in & state[4];
assign next_state[6] = in & state[5];
assign next_state[7] = in & (state[6] | state[7]);
assign next_state[8] = ~in & state[5];
assign next_state[9] = ~in & state[6];
assign out1 = (state[8] == 1'b1) || (state[9] == 1'b1);
assign out2 = (state[7] == 1'b1) || (state[9] == 1'b1);
endmodule