HDLBits-Fsm1s

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

This exercise is the same as fsm1, but using synchronous reset.

图片见题目。

module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations
    parameter A=0,B=1;
    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) begin   //在reset时，present_state=B。
            // Fill in reset logic
            present_state=B;
        end else begin
            case (present_state)
                // Fill in state transition logic
                A: next_state=in?A:B;
                B: next_state=in?B:A;
            endcase

            // State flip-flo