HDLBits学习：Fsm onehot

题目

Given the following state machine with 1 input and 2 outputs:

Suppose this state machine uses one-hot encoding, where state[0] through state[9] correspond to the states S0 though S9, respectively. The outputs are zero unless otherwise specified.

Implement the state transition logic and output logic portions of the state machine (but not the state flip-flops). You are given the current state in state[9:0] and must produce next_state[9:0] and the two outputs. Derive the logic equations by inspection assuming a one-hot encoding. (The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).

AI翻译如下

给定以下具有 1 个输入和 2 个输出的状态机：

假设此状态机使用独热编码，其中 state[0] 到 state[9] 分别对应于状态 S0 到 S9。除非另有说明，否则输出为零。

实现状态机的状态转换逻辑和输出逻辑部分（但不是状态触发器）。您将获得 state[9：0] 的当前状态，并且必须生成 next_state[9：0] 和两个输出。通过假设采用独热编码的检查来推导逻辑方程。（测试平台将使用非一个热输入进行测试，以确保您不会尝试做更复杂的事情）。

模块声明

module top_module(
    input in,
    input [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);

实现代码如下

module top_module(
    input in,
    input [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);
//定义独热码状态空间
parameter S0=10'b00_0000_0001;
parameter S1=10'b00_0000_0010;
parameter S2=10'b00_0000_0100;
parameter S3=10'b00_0000_1000;
parameter S4=10'b00_0001_0000;
parameter S5=10'b00_0010_0000;
parameter S6=10'b00_0100_0000;
parameter S7=10'b00_1000_0000;
parameter S8=10'b01_0000_0000;
parameter S9=10'b10_0000_0000;

//状态转换
assign next_state[0]=(state[0]&~in)|(state[1]&~in)|(state[2]&~in)
|(state[3]&~in)|(state[4]&~in)|(state[7]&~in)|(state[8]&~in)|(state[9]&~in);
assign next_state[1]=(state[0]&in)|(state[8]&in)|(state[9]&in);
assign next_state[2]=(state[1]&in);
assign next_state[3]=(state[2]&in);
assign next_state[4]=(state[3]&in);
assign next_state[5]=(state[4]&in);
assign next_state[6]=(state[5]&in);
assign next_state[7]=(state[6]&in)|(state[7]&in);
assign next_state[8]=(state[5]&~in);
assign next_state[9]=(state[6]&~in);

//输出
assign out1=(state==S8)|(state==S9);
assign out2=(state==S7)|(state==S9);

endmodule