Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.
前言
两个输入,包括一个时钟clk,一个高电平有效的同步置位信号reset一个输出信号q。
代码
module top_module (
input clk,
input reset,
output [3:0] q);
always@(posedge clk)begin
if(reset) q<=4'd0;
else q<= q+1'b1;
end
endmodule
总结
最简单的计数器,即时钟触发,输出+1’b1。