HDLBits 计数器

最新推荐文章于 2023-09-10 10:48:46 发布

头发是自己拔掉的

最新推荐文章于 2023-09-10 10:48:46 发布

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文章标签： fpga开发

本文链接：https://blog.csdn.net/qq_46198448/article/details/122897712

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本文详细介绍了使用HDLBits实现的各种计数器，包括4位二进制计数器、十进制计数器、带有暂停功能的计数器以及1-12计数器和频率分频器的设计。内容涵盖了同步复位、使能控制以及BCD计数器的应用，适用于FPGA开发和数字逻辑设计的学习。

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HDLBits

Count15

Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);
    always @(posedge clk) begin
        if(reset) q <= 4'h0;
        else begin
            if(q == 4'hf ) q <= 0;
            else q <= q + 4'h1;
        end
/*
	q <= q+1;		// Because q is 4 bits, it rolls over from 15 -> 0.
		// If you want a counter that counts a range different from 0 to (2^n)-1, 
		// then you need to add another rule to reset q to 0 when roll-over should occur.
*/
    end
endmodule

Count10

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.

module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);
    always @(posedge clk) begin
        if(reset | q == 4'h9) q <= 4'h0;
            else q <= q + 4'h1;
    end
endmodule

Count1to10

Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.

module top_module (
    input clk,
    input reset,
    output [3:0] q);
    always @(posedge clk) begin
        if(reset | q == 4'ha) q <= 1;
        else  q <= q + 4'h1;
    end
endmodule