Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.
Module Declaration
module top_module ( input clk, input reset, // Synchronous active-high reset output [3:0] q);
设计一个4bit的计数器,从0~15,共16个周期。reset是同步复位且复位为0。
module top_module (
input clk,
input reset, // Synchronous active-high reset
output reg [3:0] q);
always @ (posedge clk)
begin
if(reset)
q <= 4'b0000;
else
q <= q + 1'b1;
end
endmodule