【FPGA】【verilog】【基础模块】按键消抖

方案1[参考自小梅的《FPGA自学笔记》]：

module key_filter(clk,rst_n,key_in,key_flag,key_state);
	input clk;
	input rst_n;
	input key_in;
	output reg key_flag;
	output reg key_state;
	
	//----synchronize the key signal 
	reg key_in_a,key_in_b;
	always @(posedge clk or negedge rst_n)	begin 
		if (!rst_n) begin
			key_in_a <= 1'b0;
			key_in_b <= 1'b0;
		end 
		else begin 
			key_in_a <= key_in;
			key_in_b <= key_in_a;
		end 
	end 
	//------------------------------------
	
	//-------posedge detection && negedge detection-----------
	reg key_tempa,key_tempb;
	wire key_posedge,key_negedge;
	always@(posedge clk or negedge rst_n) begin 
		if (!rst_n)	begin 
			key_tempa <= 0;
			key_tempb <= 0;
		end 
		else begin 
			key_tempa <= key_in_a;
			key_tempb <= key_in_b;
		end 
	end 
	
	assign key_posedge = key_tempa		& (!key_tempb);
	assign key_negedge = (!key_tempa)	&