VLSI Design课程笔记 (上)

Overview of VLSI Design Flow

Chip manufacturing process：

$$designstyle\{\begin{array}{ll}fullcostume& \text{： }designeverything\\ standardcellbasedesign(ASIC)& \text{： }usepre-designgate\end{array}$$
full costume: minimized area, power, maximized speed, expensive and long-period
ASIC: just cheap and short-period

Cost of an Integrated Circuit

cost per IC = variable cost per IC + (fixed cost / volume)
variable cost per IC=(cost of die +cost of test +cost of packaging)/final test yield
$$\begin{gathered} finaltestYieldY=\frac{Numberofgoodchipsperwafer}{Totalnumberofchipperwafer}\ast 100\% \\ Diecost=\frac{Wafercost}{Diesperwafer\times Dieyield} \\ Diesperwafer=\frac{\pi \times (\frac{waferdiameter}{2}{)}^2}{diearea}-\frac{\pi \times waferdiameter}{\sqrt{2\times diearea}} \\ Dieyield=(1+\frac{defectsperunitarea\times diearea}{\alpha }{)}^{-\alpha } \\ \alpha \approx 3 \end{gathered}$$

Example：
we have a 4-inch wafer fab and an 8-inch wafer fab.
Calculate the cost per IC of each design at each fabrication plant (4 calculations, 2 per 4-inch and 2 per 8-inch). Identify the minimum cost fabrication facility for each design.
The microprocessor die size is 3.2 $c{m}^2$ and the projected volume is 50,000,000 units over the lifetime of the product. The cost of packaging the microprocessor is $25.00 per part, cost of testing per part is $2.78, and the non-recurring engineering design cost is $200,000,000.00.
The ASIC design is $0.25c{m}^2$ and the projected volume is only 1,000,000 units. The cost of packaging the ASIC is $0.67, cost of testing is $0.69, and the design cost is $2,000,000.00.
For both designs, the functional test yield rate is 95% and α=3. Information on the fabrication options is listed in the table below.

Ans:
Microprocessor with 4-inch wafer:
cost per IC = variable cost per IC + (fixed cost / volume)=variable cost per IC + ( $2\ast 10^8/5\ast 10^7$)
variable cost per IC= (cost of die +cost of test +cost of packaging)/final test yield
cost of test = 25
cost of packaging= 2.78
cost of die$=\frac{Wafercost}{Diesperwafer\times Dieyield}=\frac{150}{Diesperwafer\times Dieyield}$
final test yield = 95%
$Diesperwafer=\frac{\pi \times (\frac{10.16}{2}{)}^2}{3.2}-\frac{\pi \times 10.16}{\sqrt{2\times 3.2}}$
Die yield=$(1+\frac{defectsperunitarea\times diearea}{\alpha }{)}^{-\alpha }=(1+\frac{0.5\times 3.2}{3}{)}^{-3}$

Die yield=0.28
Dies per wafer=12
final test yield = 95%
cost of die=44.64
cost of packaging=2.78
cost of test = 25
variable cost per IC = 76.23
cost per IC = 76.23+ $2\ast 10^8/5\ast 10^7\approx$ $80.23

Microprocessor with 8-inch wafer:
Die yield=$(1+\frac{0.56\times 3.2}{3}{)}^{-3}$= 0.245
Dies per wafer=$\frac{\pi \times (\frac{20.32}{2}{)}^2}{3.2}-\frac{\pi \times 20.32}{\sqrt{2\times 3.2}}$= 76
final test yield = 95%
cost of die=$\frac{800}{76\times 0.25}$=42.9
cost of packaging=2.78
cost of test = 25
variable cost per IC = (42.9+2.78+25) / 0.95 = 73.45
cost per IC = 74.45+ $2\ast 10^8/5\ast 10^7\approx$ $78.45

ASIC with 4-inch wafer:
cost per IC = variable cost per IC + (fixed cost / volume)=variable cost per IC + ( $2\ast 10^6/10^6$)
variable cost per IC= (cost of die +cost of test +cost of packaging)/final test yield
cost of test = 0.69
cost of packaging= 0.67
cost of die$=\frac{Wafercost}{Diesperwafer\times Dieyield}=\frac{150}{Diesperwafer\times Dieyield}$
final test yield = 95%
$Diesperwafer=\frac{\pi \times (\frac{10.16}{2}{)}^2}{0.25}-\frac{\pi \times 10.16}{\sqrt{2\times 0.25}}$
Die yield=$(1+\frac{defectsperunitarea\times diearea}{\alpha }{)}^{-\alpha }=(1+\frac{0.5\times 0.25}{3}{)}^{-3}$

Die yield=0.88
Dies per wafer= 279
final test yield = 95%
cost of die= 0.61
cost of packaging=0.69
cost of test = 0.67
variable cost per IC = 2.07
cost per IC = 2.07+ $2\ast 10^6/10^6\approx$ $4.07

ASIC with 8-inch wafer:
Die yield=$(1+\frac{0.56\times 0.25}{3}{)}^{-3}$= 0.87
Dies per wafer=$\frac{\pi \times (\frac{20.32}{2}{)}^2}{0.25}-\frac{\pi \times 20.32}{\sqrt{2\times 0.25}}$= 1206
final test yield = 95%
cost of die=$\frac{800}{1206\times 0.87}$= 0.76
cost of packaging= 0.69
cost of test = 0.67
variable cost per IC = (0.76+0.69+0.67) / 0.95 = 2.23
cost per IC = 2.23+ $2\ast 10^8/10^6\approx$ $4.23

A new 12-inch fabrication facility for production of the microprocessor part. The 12-inch fabrication facility will cost an additional $1,000,000,000.00 to construct for this project. Develop a constraint on the defect density of this new facility that will ensure cost savings over the previous minimum cost solution. Volume cost for 12-inch wafers is estimated to be
$1500/wafer.

Microprocessor with 12-inch wafer(new):
find defect density $x$
Die yield=$(1+\frac{x\times 3.2}{3}{)}^{-3}$
Dies per wafer=$\frac{\pi \times (\frac{30.48}{2}{)}^2}{3.2}-\frac{\pi \times 30.48}{\sqrt{2\times 3.2}}$= 190
final test yield = 95%
cost of die=$\frac{1500}{190\times Dieyield}$
cost of packaging=2.78
cost of test = 25
variable cost per IC = (cost of die+2.78+25) / 0.95
cost per IC = variable cost per IC+ $(2\ast 10^8+10^9)/5\ast 10^7<$ $78.45

$defectdensityx\le 0.42$

Fan-out： the number of load gates $N$ that are connected to the output of the
driving gate
Fan-in: the number of inputs to the gate

propagation delay $t_p$:how quickly it responds to a change at its input(s)
measured between the 50% transition points of the input and output waveforms

$$t_p=\frac{t_{pHL}+t_{pLH}}{2}$$

Period of ring oscillator $T$

odd number($N$) of inverter
$$T=2\times t_p\times N$$

noise margin

$V_{OH}$: Maximum output voltage when the output level is logic “1”
$V_{OL}$: Maximum output voltage when the output level is logic “0”
$V_{IL}$: Maximum input voltage which can be interpreted as logic “0”
$V_{IH}$: Maximum input voltage which can be interpreted as logic “1”

Propagation delay of First-order RC network

The time to reach the 50% point: $t=ln(2)\tau =0.69\tau$
Time to the 90% point: $t=ln(9)\tau =2.2\tau$
$\tau =RC,timeconstant$
logic change from 0 to 1, this process needs power: $E_{0\to 1}=C_L\cdot V_{dd}^2$
logic change from 1 to 0 do not need energy
power dissipation of capacitor: $E_{cap}=\frac{1}{2}{C}_L\cdot V_{dd}^2$

CMOS Fabrication Process Technology

Photolithography： The technique to accomplish selective masking so that a desired processing step can be selectively applied to the remainingregions.
Photolithography invovle:

1. Oxidation layering
2. Photoresist coating
3. Stepper exposure
4. Photoresist development and bake
5. Acid Etching
6. Spin, rinse, and dry
7. Various process steps
8. Photoresist removal (or ashing)

Some important techniques used：Diffusion and Ion Implantation, Deposition, Etching, Planarization

Simplified process:

MOS Transistor Theory

static behaviour

Built-in potential: under zero bias, there exists a voltage ${\varphi }_0$ across the junction. $${\varphi }_0={\varphi }_{T}ln[\frac{N_A{N}_D}{n_i^2}]$$ $n_i$: intrinsic carrier concentration in a pure sample of the semiconductor and equals approximately $1.5\ast 10^{10}c{m}^{-3}$ at 300 K for silicon.

Ideal diode equation: $$I_D=I_S(e^{V_D/{\varphi }_T}-1)$$ ${\varphi }_T$: termal voltage, equal to 26 mV at room temperature.
$I_S$: saturation current, constant value.

Junction Capacitance: the space-charge region contains few mobile carriers, it acts as an insulator with a dielectric constant ${\epsilon }_{si}$ of the semiconductor material. The n- and p-regions act as the capacitor plates. $$C_j=\frac{C_{j0}}{(1-V_D/{\varphi }_0{)}^m}$$ $m=0.5$ :abrupt junction
$m=0.33$ :linear junction
$C_{j0}$: the capacitance under zero-bias conditions, $C_{j0}=A_D\sqrt{(\frac{{\epsilon }_{si}q}{2}\frac{N_A{N}_D}{N_A+N_D}){\varphi }_0^{-1}}$
${\varphi }_0$: Built-in potential (defined previously)

MOS Transistor under Static Conditions

Threshold Voltage:$$V_T=V_{T0}+\gamma \ast (\sqrt{|-2{\varphi }_F+V_{SB}|}-\sqrt{|-2{\varphi }_F|})$$
$V_{T0}$: Threshold voltage for substrate bias voltage $V_{SB}=0$
${\varphi }_F$: Fermi Potential, ${\varphi }_F=-{\varphi }_{T}ln(\frac{N_A}{n_i})$, sometimes 0.55V
$N_A$: substrate doping
$\gamma$: body-effect coefficient, $\gamma =\sqrt{2q{N}_A{\epsilon }_{Si}}/C_{ox}$

the voltage-current relation of the transistor in linear region/resistive region ($V_{DS}<V_{GS}-V_T$)$$\begin{gathered} I_D=k_n^{\prime }\frac{W}{L}[(V_{GS}-V_T)V_{DS}-\frac{V_{DS}^2}{2}] \\ =k_n[(V_{GS}-V_T)V_{DS}-\frac{V_{DS}^2}{2}] \end{gathered}$$
the voltage-current relation of the transistor in saturation region($V_{DS}>V_{GS}-V_T$)$$I_D=\frac{k_n^{\prime }}{2}\frac{W}{L}(V_{GS}-V_T{)}^2$$
$k_n^{\prime }$: process transconductance parameter, $k_n^{\prime }={\mu }_n{C}_{ox}$
${\mu }_n$: mobility parameter, expressed in $m^2/V\cdot s$
$C_{ox}$: capacitance per unit area presented by the gate oxide. $C_{ox}=\frac{{\epsilon }_{ox}}{t_{ox}}$
${\epsilon }_{ox}$: oxide permittivity, $3.5\times 10^{-11}$
$t_{ox}$: thickness of the oxide
$k_n$: gain factor
$W$: channel width
$L$: channel length
$V_{GS}$: voltage apply between gate and source
$V_{DS}$: voltage apply between drain and source
$V_T$:threshold voltage (define previously)

channel length modulation
increasing $V_{DS}$ causes the depletion region at the drain junction to grow,reducing the length of the effective channel, the current increases when the length factor $L$ decrease
$$I_D=I_D^{\prime }(1+\lambda V_{DS})$$ $I_D^{\prime }$: the current expressions derived earlier
$\lambda$: empirical parameter

short channel effect

• velocity saturation
• subthreshold current
• hot electron
• DIBL: brain induced barrier lowering

velocity saturation:

when the electrical field along the channel reaches a critical value ${\xi }_c$, the velocity of the carriers tends to saturate due to scattering effects.
Velocity-saturation effects are more pronounced in NMOS short-channel transistors.
drain current in the resistive/linear region with velocity saturation effect
$$\begin{gathered} I_{DSAT}={\upsilon }_{sat}{C}_{ox}W((V_{GS}-V_T)-V_{DSAT}) \\ =\kappa (V_{DSAT}){\mu }_n{C}_{ox}\frac{W}{L}[(V_{GS}-V_T)V_{DSAT}-\frac{V_{DSAT}^2}{2}] \\ {V}_{DSAT}=\kappa (V_{GS}-V_T)(V_{GS}-V_T)=L{\xi }_c \end{gathered}$$

${\upsilon }_{sat}$: saturation velocity, $={\mu }_n{\xi }_c$, approximately equals $10^5$ m/s.
$\kappa (V_{DSAT})$: $=\frac{1}{1+(V_{DSAT}/{\xi }_{c}L)}$, measure of the degree of velocity saturation

subthreshold conduction
the current does not drop abruptly to 0 at $V_{G}S=V_T$. MOS transistor is already partially conductiong for voltages below the threshold voltage. This effect is called subthreshold or weak-inversion conduction.
current in subthreshold exponential region:$$I_D=I_S{e}^{\frac{V_{GS}}{nkT/q}(1-e^{\frac{V_{DS}}{kT/q}})}$$
$I_S,n$: empirical parameters
slope factor $S$: inverse rate of decline of the current with respect to $V_{G}S$ below $V_T$, measures by how much $V_{G}S$ has to be reduced for the drain current to drop by a factor of 10:$$S=n(\frac{kT}{q})ln10$$
unit:$mV/decade$

hot electron/ hot carrier
Caused by high electric fields. Electrons and holes gaining high kinetic energies in the electric field (hot carriers) may be injected into the gate oxide, and cause permanent changes in the oxide-interface charge distribution, degrading the current-voltage characteristics of the MOSFET.

DIBL: drain-induced barrier lowering
If the drain voltage is increased, the potential barrier in the channel decreases, leading to drain-induced barrier lowering. The reduction of the potential barrier eventually allows electron flow between the source and the drain, even if the gate-to-source voltage is lower than the threshold voltage. The channel current that flows under these conditions ($V_{GS}<V_{T0}$) is called the sub-threshold current.

dynamic behaviour

channel capacitance
total: $C=C_{ox}\cdot W\cdot L_D$
$C_{ox}$:gate oxide capacitance per unit area
$W$: channel width
$L_D$: lateral diffusion

operation region	$C_{gs}$- between gate and source	$C_{gd}$- between gate and drain	$C_{gb}$- between gate and body
Cutoff	0	0	$C_{ox}W(L-2L_D)$
Resistive/linear	$\frac{1}{2}{C}_{ox}W(L-2L_D)$	$\frac{1}{2}{C}_{ox}W(L-2L_D)$	0
Saturation	$\frac{2}{3}{C}_{ox}W(L-2L_D)$	0	0

$L-2L_D$: effective channel length

p-mos pull up; n-mos pull down

Source-drain Resistance
$$R_{S,D}=R_{\square }\frac{L_{S,D}}{W}+R_C$$
$L_{S,D}$: length of the source or drain region
$W$: width of the transistor
$R_{\square }$: sheet resistance
$R_C$: contact resistance

Circuit Characteristic and Performance Estimation

latch up

must be prevented by reducing substrate noise, it will ruin all devices

Why latch up will cause problem: the creation of a low-impedance possitive-feedback path between power supply rails as a result of triggering a parasitic device. The noise in this circuit will be amplifid and produce excessisve current.

wire capacitancce

capacitance of wire interconnect:
wire parallel plate capacitance: $C=\frac{{\epsilon }_{ox}}{t_{ox}}(W\ast L)$
L: wire length
W: wire width

$C_{total}=C_{parallel}+C_{fringe}=\frac{w{\epsilon }_{ox}}{t_{ox}}+\frac{2\pi {\epsilon }_{ox}}{lg(t_{ox}/H)}$
H: interconnect thickness
$w$: $w=W-H/2$

$\frac{{\epsilon }_{ox}}{t_{ox}}$. area capacitance(parallel-plate) are expressed in $aF/\mu m^2$, while the fringe capacitance(given in the shaded rows) are in $aF/\mu m$

wire resistance
$R=\frac{\rho L}{HW}=R_{\square }\frac{L}{W}$

resistance (per unit length) at high frequencies(with skin effect, consider skin depth)$$r(f)=\frac{\sqrt{\pi f\mu \rho }}{2(H+W)}$$
$\mu$: permeability of the surrounding dielectric, $4\pi \times 10^{-7}H/m$

lumped model

how to calculate RC delay of a tree-structured network

$$\tau =C_1{R}_1+C_2(R_1+R_2)+C_3(R_1+R_3)+C_4(R_1+R_3+R_4)+C_i(R_1+R_3+R_i)$$

$${\tau }_{SD}=C_1{R}_1+C_2(R_1+R_2)+C_3(R_1+R_2+R_3)+C_4(R_1+R_2+R_3)+C_5{R}_1+C_6{R}_1+C_7(R_1+R_2)+C_8(R_1+R_2+R_3)$$

Time-Constant of Resistive-Capacitive Wire
${\tau }_{DN}=RC\frac{N+1}{2N}=rc{L}^2\frac{N+1}{2N}$
wire delay:$\frac{rc}{2}{l}^2$
$r$: resistance per unit length
$c$: capacitance per unit length

9 stages or 11 stage RC
simplified model: $\pi$ model or T model

in a chip:
top layer is the most thick layer
global signal travel same distance
If gate delay>wire delay, we can ignore wire delay

*diffusion equation of voltage node at node i of distributed RC line *$$\frac{{\partial }^{2}V}{\partial x^2}=rc\frac{\partial V}{\partial t}$$

impedence of transmission line is not related to the length
impedence: $$Z=\frac{Z_L-Z_0}{Z_L+Z_0}$$
$Z_L$: load
$Z_0$: characteristic impedence
telegraph equation:
$$V_r=(\frac{Z_L-Z_0}{Z_L+Z_0})V_{i}n$$
when impedence matching: $V_r=0$

lattice diagram

Reflection Coefficient:
$$\begin{gathered} T_{Z_L}=\frac{Z_L-Z_0}{Z_L+Z_0}={\rho }_L \\ {T}_{Z_S}=\frac{Z_S-Z_0}{Z_S+Z_0}={\rho }_S \end{gathered}$$
incoming signal:
$$V_{in}=\frac{Z_0}{Z_S+Z_0}{V}_s=V_{initial}$$
$(R_L=Z_L;R_S=Z_L)$

$$\begin{gathered} a=V_{initial} \\ b=a{\rho }_L \\ c=b{\rho }_s \\ d=c{\rho }_L \\ e=d{\rho }_s \\ f=e{\rho }_L \end{gathered}$$

example:
$R_S=5Z_0,R_L=\infty ,V_S=5V$
$$\begin{gathered} a=V_{initial}=\frac{Z_0}{Z_S+Z_0}{V}_s=\frac{1}{6}\ast 5V=0.8333V \\ {\rho }_L=\frac{Z_L-Z_0}{Z_L+Z_0}=1 \\ b=a{\rho }_L=\frac{5}{6}\ast 1=0.8333V \\ {\rho }_S=\frac{Z_S-Z_0}{Z_S+Z_0}=\frac{2}{3} \\ c=b{\rho }_s=\frac{5}{6}\ast \frac{2}{3}=0.5556 \\ d=c{\rho }_L=\frac{5}{9}\ast 1=0.5556 \\ e=d{\rho }_s=\frac{5}{9}\ast \frac{2}{3}=0.3704 \\ f=e{\rho }_L=0.3704g=f{\rho }_s=0.2469 \\ h=g{\rho }_L=0.2469 \end{gathered}$$
$$\begin{gathered} A=a=0.8333 \\ B=a+b+c=2.2216 \\ C=a+b+c+d+e=3.1476 \end{gathered}$$
$$\begin{gathered} A^{\prime }=a+b=1.6666 \\ {B}^{\prime }=a+b+c+d=2.7772 \\ {C}^{\prime }=a+b+c+d+e+f=3.5180 \end{gathered}$$

example:
$R_S=75\Omega ,Z_0=50\Omega ,R_L=\infty ,V_S=2V$
$$\begin{gathered} a=V_{initial}=\frac{Z_0}{Z_S+Z_0}{V}_s=\frac{2}{5}\ast 2V=0.8V \\ {\rho }_L=\frac{Z_L-Z_0}{Z_L+Z_0}=1 \\ b=a{\rho }_L=\frac{4}{5}\ast 1=0.8V \\ {\rho }_S=\frac{Z_S-Z_0}{Z_S+Z_0}=\frac{1}{5} \\ c=b{\rho }_s=\frac{4}{5}\ast \frac{1}{5}=0.16 \\ d=c{\rho }_L=0.16\ast 1=0.16 \\ e=d{\rho }_s=0.16\ast \frac{1}{5}=0.032 \\ f=e{\rho }_L=0.032 \end{gathered}$$
$$\begin{gathered} A=a=0.8 \\ B=a+b+c=1.96 \\ C=a+b+c+d+e=2.152 \end{gathered}$$
$$\begin{gathered} A^{\prime }=a+b=1.6 \\ {B}^{\prime }=a+b+c+d=1.92 \\ {C}^{\prime }=a+b+c+d+e+f=1.984 \end{gathered}$$

Circuit Simulation and Combinational Circuit Design

CMOS saturation diagram of NOT gate

$V_{IL}:$ PMOS in linear NMOS in saturation
$V_{IH}:$ PMOS in saturation NMOS in linear
$V_{OH}:$ PMOS in linear NMOS off
$V_{OL}:$ PMOS off NMOS linear

at middle point ©, $V_{in}=V_{out}=V_{TL}(logicthreshold)=\frac{V_{DD}}{2}$
$$k_R=\frac{k_n}{k_p}$$

for fast raise time and middle logic threshold point: $\frac{w_p}{L_n}=2.5\ast \frac{w_n}{L_n}$

multi-stage fanout

capacitance between driver and receiver: $C_L{=}_{gsp}+c_{gdp}+c_{gdn}+c_{gsn}+c_w$
$C_{gp}=2.5C_{gn}$
total delay: ${\tau }_p=0.69c_L(\frac{R_{eqN}+R_{eqP}}{2})$
width:$w_p=\beta \ast w_n$
$t_p=0.345[(1+\beta )(c_{gdN}+c_{gsN})+c_w]R_{eqN}(1+\beta )$
$\tau ={\tau }_{int}+S\cdot C_L$
$t_p=0.69R_{eq}{c}_{int}(1+C_{ext}/C_{int})$
$C_{ext}$: external load capacitance

energy store in cap
$$\frac{1}{2}{C}_L{V}_{DD}^2$$

if we need big driver, we should gradually increase size of TR, optimize total delay gate 1 gate 2 gate 3 gate 4 … gate n
$\tau =N\cdot R_{1}S{C}_1$
$R_1$: the resistor of the first transistor
$C_1$: capacitor of the first transistor

maximum number of fan-out(also the minimum delay): 4

sizing factor $F$ and effective fanout$f$
$$f=\sqrt[N]{C_L/C_{g,1}}=\sqrt[N]{F}$$
$N$: number of fan-out
$C_{g,1}$:input capacitance of the first inverter (minimally-sized device)
minimum delay
$t_p=N{t}_{p0}(1+\sqrt[N]{F}/\gamma )$
$t_{p0}$: intrinsic delay of inverter (independent of sizing)
$\gamma$: $\frac{c_{int}}{c_g}$, proportionality factor, which is only a function of technology and is close to 1

fanout for best power consumption

$$\begin{gathered} C_{tot}=C_{g1}[(1+\gamma )(1+f)+F] \\ \text{energy dissipation:} \\ E=V_{dd}^2{C}_{g1}((1+\gamma )(1+f)+F) \end{gathered}$$

CMOS circuit power consumption

• dynamic power/switching power
• short circuit power
• leakage power/static power
  • subthreshold current
  • BTBT current (diode leakage current)
  • Gate tunneling

energy consumed per switching period:
$$E_{dp}=t_{sc}{V}_{DD}{I}_{peak}$$
$t_{s}c$: time both devices are conducting, $\frac{V_{DD}-2V_T}{V_{DD}}{t}_{rising}$
average power consumption:
$$P_{dp}=C_{sc}{V}_{DD}f$$

power delay product PDP
$$C_L{V}_{DD}^2/2$$
energy delay product EDP
$$PDP\ast t_p=\frac{\alpha \ast C_L^2{V}_{DD}^3}{2(V_{DD}-V_T)}$$
$\alpha$: technology parameter

techniques to reduce power

• MTVT: multi-threshold voltage technique
• clock gating
  • pipelining
  • parallel processing
• coding technique
  • thermometer code

MTVT: threshold voltage higher, harder to turn on transistor, react slower, but less leakage (high threshold can reduce leakage).

technology scaling

Parameter	Relation	Full Scaling	General scaling	Fixed-Voltage scaling
Area/Device	$WL$	$1/S^2$	$1/S^2$	$1/S^2$
Intrinsic Delay	$R_{on}{C}_{gate}$	$1/S$	$1/S$	$1/S$
Intrinsic Energy	$C_{gate}{V}^2$	$1/S^3$	$1/S{U}^2$	$1/S$
Intrinsic Power	Energy/Delay	$1/S^2$	$1/U^2$	1
Power Density	P/Area	1	$S^2/U^2$	$S^2$

(未完)