【模电读书笔记】CHAPTER 2 Diode Applicatoions

最新推荐文章于 2024-08-11 23:46:27 发布

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最新推荐文章于 2024-08-11 23:46:27 发布

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Load-line analysis

load-line analysis: If the analysis is performed in a graphical manner, a line can be drawn on the characteristics of the device that represents the applied load. The intersection of the load line with the characteristics will determine the point of operation of the system. 图形化分析中，在器件特性曲线图上画一条代表负载的线，该线与特性曲线的交点可以确定工作点。

network & characteristics of diode.
in the series circuit:
$E=V_D+I_DR\\ I_D=\frac E R |_{V_D=0V}\\ V_D=E |_{I_D=0A}$
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Q-point/ quiescent point/ Q-pt: point of operation,

Series diode configurations with DC inputs

substituing the equivalent model for the “on” diode of an ideal Si diode. $V_T$ of an ideal Si diode usually is 0.7V.
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$V_D=V_T\\ V_R=E-V_T\\ I_D=I_R=\frac {V_R} R$

Sinusoidal inputs; half-wave rectification

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half-wave rectifier: use in the ac-to-dc conversion, removing one-half the input signal to establish a dc level
$V_{dc}=0.318V_m$

PIV/PRV: peak inverse(reverse) voltage
$\;rating\ge V_m$ (for half-wave rectifier), otherwise the diode will enter Zener region.

Full-wave rectification.

bridge network

Full-wave bridge rectifier
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During the period $t = 0$ to $\frac T2$
During the period $t=\frac T2 to \;T$

full-wave dc level output: $V_{dc}=0.636V_m$

PIV of full-wave bridge rectifier: $PIV\ge V_m$

center-tapped transformer

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positive portion	negative portion

PIV of center-tapped rectifier: $PIV\ge 2V_m$

clipper

parallel clipper

the diode is in parallel with the load
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series clipper

the diode is in series with the load
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clipper summary

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clampers

for clamping network, the total swing of the output is equal to the total swing of the input signal. 输出信号的总摆幅等于输入信号的总摆幅。

Zener Diodes

齐纳二极管的稳压应用：

$V_i$ and R fixed 输入电压和负载固定

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$V=V_L=\frac {R_LV_i}{R+R_L}$

fixed $V_i$ , variable $R_L$ 输入电压固定，负载可变

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$R_{L_{min}}=\frac {RV_z}{V_i-V_z}\\ R_{L_{max}}=\frac {V_Z}{I_{L_{min}}}$

fixed $R_L$ , variable $V_i$ 负载固定，输入电压可变

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$V_{i_{min}}=\frac {(R_L+R)V_z}{R_L}\\ V_{i_{max}}=I_{R_{max}}R+V_z$

VOLTAGE MULTIPLIER CIORCUITS

voltage doubler

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positive half-cycle: D1 conduct, D2 open, C1 charge to Vm
negative half-cycle: C1 discharge, D1 open D2 conduct, C2 charge to 2Vm
next positive half-cycle: C2 discharge to the load(if exist)

full-wave doubler:
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positive half-cycle: D1 on, D2 off, C1 charge to Vm
negative half-cycle: D1 off, D2 on, C2 charge to Vm

voltage tripler and quadrupler

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1st postive half-cycle: C1 charge through D1 to Vm
1st negative half-cycle: C2 charge through 2Vm through D2
2nd positive half-cycle: C3 charge to 2Vm by C2 through D3
2nd negative half-cycle: C4 charge to 2Vm by C3 through D2 D4