【模电读书笔记】CHAPTER 4 DC Biasing——BJTs

Operating point

operating point/ quiescent point/ Q-point: define the region that will be employed for amplification of the applied signal. 静态工作点： 定义了对目的信号进行放大的区域

maximum ratings: the maximum collector current $I_{C_{max}}$ and maximum collector-to-emitter voltage $V_{C{E}_{max}}$. 最大集电极电流和最大集电极-发射极电压

maximum power constrain最大功率限制: defined by the curve $P_{C_{max}}$

cutoff region截止区域: defined by $I_B\le 0$
saturation region饱和区域: $V_{CE}\le V_{C{E}_{max}}$

no bias — device off, Q-point at A, zero current and voltage
signal applied: device react to(amplify) input signal

conditions that make sure the BJT to be biased in its linear or active operating region使得BJT工作在线性放大区域的条件:

1. base-emitter junction must be forward-biased, with a resulting forward-bias voltage of about 0.6 to 0.7V. 发射结正偏，正偏电压0.7V左右。
2. base-collector junction must be reverse-biased with the reeverse-bias voltage being any value within the maximum limits of the device. 集电结反偏，且反偏电压不超过限制。

the BJT characteristic when operating in the cutoff, saturation and linear regions

	linear region	cutoff region	saturation region
Base-emitter junction	forward biased	reverse biased	forward biased
Base-collector junction	reverse biased	\	forward biased

fixed-bias circuit

forward bias of base-emitter

$$I_B=\frac{V_{CC}-V_{BE}}{R_B}$$

Collector-Emitter loop

if emitter connect to the ground
$$\begin{gathered} V_{CE}=V_{CC}-I_C{R}_C \\ {V}_{CE}=V_C \\ {V}_{BE}=V_B \end{gathered}$$

transistor saturation

For a transistor operating in the saturation region, the current is a maximum value for the particular design. The highest saturation level is defined by the maximum collector current.
对于一个工作在饱和区的晶体管， 电流达到其最大值。 最大饱和水平由最大集电极电流定义。

to determine $I_{C_{sat}}$, assuming $V_{CE}=0V$

$$I_{C_{sat}}=\frac{V_{CC}}{R_C}$$

LOAD-LINE Analysis

draw line $V_{CE}=V_{CC}-I_C{R}_C$ on the resistor characteristics:

the slope line on the graph call the load line, it is defined by the load resistor $R_C$

Emitter-Stabilized bias circuit

base-emitter loop

$$I_B=\frac{V_{CC}-V_{BE}}{R_B+(1+\beta )R_E}$$

the emitter resistor, which is part of the collector-emitter loop, “appears as” $(\beta +1)R_E$ in the base-emitter loop。射极电阻作为集电极-射极回路的一部分，在基极-发射极回路中“显示”为$(\beta +1)R_E$
$$R_i=(\beta +1)R_E$$

Collector-Emitter Loop

$$\begin{gathered} V_{CE}=V_{CC}-I_C(R_C+R_E) \\ {V}_E=I_E{R}_E \\ {V}_C=V_{CC}-I_C{R}_C \\ {V}_B=V_{BB}-I_B{R}_B \end{gathered}$$

Saturation level

Apply a short circuit between the collector-emitter terminals 假设集电极和发射极之间短路
$$I_{C_{sat}}=\frac{V_{CC}}{R_C+R_E}$$

Load-Line Analysis

$$V_{CE}=V_{CC}-I_C(R_C+R_E)$$

Voltage-Divider Bias

a bias circuit that is less dependent on $\beta$(temperature sensitive):

Analysis:

$$R_{Th}=R_{1}parallelwith{R}_2$$
Thevenin voltage:
$$\begin{gathered} E_{Th}=\frac{R_2{V}_{CC}}{R_1+R_2} \\ {I}_B=\frac{E_{Th}-V_{BE}}{R_{Th}+(\beta +1)R_E} \\ {V}_{CE}=V_{CC}-I_C(R_C+R_E) \end{gathered}$$

if $R_i=(\beta +1)R_E$ is much larger than $R_2$, the current $I_B$ will be much smaller than $I_2$ and $I_2$ will be approximately equal to $I_1$
$$\begin{gathered} if\beta R_E\ge 10R_2: \\ {V}_B=\frac{R_2{V}_{CC}}{R_1+R_2} \\ {I}_E=\frac{V_E}{R_E} \\ {I}_{C_Q}\approx I_E \\ {V}_{C{E}_Q}=V_{CC}-I_C(R_C+R_E) \end{gathered}$$