uvm_reg_field

1 uvm_reg_field

1.1 configure

function void configure(
   		uvm_reg 	parent,
   		int 	unsigned 	size,
   		int 	unsigned 	lsb_pos,
   		string 				access,
   		bit 				volatile, //易失存储器
   		uvm_reg_data_t 		reset,
   		bit 				has_reset,
   		bit 				is_rand,
   		bit 				individually_accessible
);

1.2 write

task uvm_reg_field::write(output uvm_status_e       status,
                          input  uvm_reg_data_t     value,
                          input  uvm_path_e         path = UVM_DEFAULT_PATH,
                          input  uvm_reg_map        map = null,
                          input  uvm_sequence_base  parent = null,
                          input  int                prior = -1,
                          input  uvm_object         extension = null,
                          input  string             fname = "",
                          input  int                lineno = 0);

1.3 read

task uvm_reg_field::read(output uvm_status_e       status,
                         output uvm_reg_data_t     value,
                         input  uvm_path_e         path = UVM_DEFAULT_PATH,
                         input  uvm_reg_map        map = null,
                         input  uvm_sequence_base  parent = null,
                         input  int                prior = -1,
                         input  uvm_object         extension = null,
                         input  string             fname = "",
                         input  int                lineno = 0);

2 uvm_reg

2.1 new()

// function new
// 
// 'n_bits' specifies the total number of bis in the register
// 'has_coverage' specifies which functional coverage models are present in the extension of the register abstraction class
function new(string name="",int unsigned n_bits,int has_coverage);
endfunction 

typedef enum{
    UVM_NO_COVERAGE,
    UVM_CVR_REG_BITS,
    UVM_CVR_ADDR_MAP,
    UVM_CVR_FIELD_VALS,
    UVM_CVR_ALL
}

2.2 configure

local uvm_reg_block m_parent;
local uvm_reg_file m_reg_file_parent;



function void configure(uvm_reg_block blk_parent,
                        uvm_reg_file regfile_parent = null,
                        string hdl_path = ""
   	                    );
    m_parent = blk_parent;
    m_parent.add_reg(this);
    m_regfile_parent = regfile_parent;
    if(hdl_path != "")
        add_hdl_path_slice(hdl_path,-1,-1);
endfunction

3 uvm_reg_block

3.1 create_map

// name: map的名字
// base_addr- all registers,memories within the map will be at offset to this address
// n_bytes: the byte-width of the bus on which this map is used - 总线宽度，以byte为单位
// endian: 寄存器的存储方式是大端模式还是小端模式
// byte_addressing: 
function uvm_reg_map create_map(string name,
                                uvm_reg_addr_t base_addr,
                                int unsigned n_bytes,
                                uvm_endianness_e endian,
                                bit byte_addresssing=1
								)
	uvm_reg_map map;
    if (this.locked) begin
      `uvm_error("RegModel", "Cannot add map to locked model");
      return null;
   	end
    
    map = uvm_reg_map::type_id::create(name,,this.get_full_name());
    map.configure(this,base_addr,n_bytes,endian,byte_addressing);
    this.map[map] = 1;
    if(map.num() == 1)
        default_map = map;
    return map;
endfunction

3.1 add_reg

local static id;
local int unsigned regs[uvm_reg]; // An interger array with uvm_reg handle index
logic bit maps[uvm_reg_map];
local bit locked;
//default map 
uvm_reg_map default_map;

function void add_reg(uvm_reg rg);
    if(this.is_locked()) begin 
        `uvm_error("RegModel","Can not add register to locked block model")
       	return;
    end
    
    if(this.regs.exists(rg)) begin 
 		`uvm_error("RegModel", {"Register '",rg.get_name(),
         "' has already been registered with block '",get_name(),"'"})
        return;
    end
    regs[rg] = id++;
endfunction 

3.3 lock_model

function bit is_lock();
    return this.locked;
endfunction 

function void locked_model();
    if(is_locked())
        return
    locked = 1;
    
   	...
endfunction

与寄存器相匹配，内部可以例化和配置多个uvm_reg_field

每个派生自uvm_reg 的类都有一个build方法，该方法不会自动执行，需要手动调用；在build 方法中主要实现uvm_reg_field的例化和配置( configure())

4 uvm_reg_map

作用：寄存器的地址映射，等效于硬件电路的地址译码。

4.1 add_reg()

virtual function void add_reg(
	uvm_reg 	   rg,
    uvm_reg_addr_t offset,
    string rights = "RW",
    bit    unmapped = 0,
    uvm_reg_frontdoor frontdoor=null
)

将实例化的寄存器模型加入到uvm_reg_map中，使得通过map索引到寄存器模型。相关参数如下：

• rg 加入到map的寄存器模型
• offset 表示寄存器的偏移地址
• rights 表示寄存器的读写方式

class hierarchy

uvm_void -> uvm_object -> uvm_reg_map

The class represents an address map that is a collection of registers and memories.

method：

set_sequencer(sequencer,adapter)

作用: 通过register map 中的set_sequencer完成adapter与sequencer的连接，

5 uvm_reg_predictor

作用：通过监测总线上寄存器的操作，从而更新寄存器模型内的值。

class uvm_reg_predictor #(type BUSTYPE=int) extends uvm_component;

存在两种预测方法：

• 隐式预测（implicit prediction）

map 默认的一种prediction方式，主要利用寄存器的操作自动记录寄存器读写值，然后通过后台自动调用predict()方法。

• 显示预测 (explicit prediction)

将monitor监测的总线事务传递给predictor, 利用adapter 将总线事务转化为寄存器事务，最终更新寄存器模型。

6 adapter

作用： 完成寄存器访问事务与总线事务的相互转换，主要实现函数为reg2bus和bus2reg

reg2bus

pure virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);

bus2reg

pure virtual function bus2reg(uvm_sequence_item,ref uvm_reg_bus_op rw);

附图：

在这里插入图片描述