【UVM】reg_model的一些基本操作

UVM的寄存器模型,对一个寄存器bit中有两种数值,mirror值,尽可能的反映DUT中寄存器的值。expected值,尽可能的反映用户期望的值。

几种常用的操作:

read/write:可以前门访问也可以后门访问,如果在env的顶层定义过uvm_auto_predict(1),则UVM会在这两个操作后自动调用do_predict函数来更新寄存器模型中的mirror值。

peek/poke:只用于后门访问,而且完全不管硬件的行为,如向只读寄存器写数据,仍可以写入。应用很少。会自己更新mirror值和expected值。

get/set:得到或设置寄存器模型的期望值。

update操作:可以使用前门访问,也可以使用后门访问,检查期望值与镜像值是否一致,如不一致,则向DUT写入期望值。 通过枚举结构uvm_path_e来定义。

mirror操作:用于读取DUT中寄存器的值并将它们更新到寄存器模型中。可以前门访问也可以后门访问。两种的应用场景:1)check选项关闭,仿真中不断调用。2)check选项打开,用在结束时,检查DUT与寄存器模型的值是否相同。

predict操作:人为的根据DUT来更新寄存器模型中的镜像值。但同时又不对DUT进行任何操作。此时的uvm_path_e是UVM_PREDICT_DIRECT。可以通过加monitor在寄存器总线上。检测到uvm_reg_item操作,便通过TLM传送到uvm_reg_predict模块来更新mirror值。函数内部主要有do_predict操作,这是主要的实现函数。还有一个post_predict的回调函数,可以自己扩展根据mirror值更新期望值。但是pre_predict并不是一个回调函数,仅仅只是一个虚函数原型。可以在do_predict操作之前调用,完成覆盖率采样。

 

由于前门访问会消耗仿真时间,而后门访问不会消耗仿真时间,所以在build_phase,connect_phase只能使用后门访问,所以uvm_path_e中默认定义有一个UVM_DEFAULT_PATH,这样就可以在这些phase隐式的指明后门访问。而在task phase中在显式的指明前门访问。(这时DUT已经开始工作,使用前门访问比较接近硬件)一般在config中使用寄存器模型,先set/randomized再update。后门访问。

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UVM (Universal Verification Methodology) provides a set of classes and macros to facilitate verification of hardware designs. One of the key components in UVM is the register model, which represents the registers and memories in the design. UVM provides a callback mechanism called UVM Callbacks (uvm_callbacks) to handle events and actions during the register access process. UVM register callbacks (uvm_reg_cbs) are a specific type of callback used for registering certain events related to register accesses. UVM register callbacks allow users to customize and extend the behavior of UVM register operations. These callbacks can be used to perform additional tasks before or after register read/write operations, such as logging, synchronization, or checking certain conditions. To use UVM register callbacks, you need to define a class derived from uvm_reg_callback and implement the desired callback methods. These methods will be called by UVM framework when corresponding events occur during register access. Here's an example of using UVM register callbacks: ```systemverilog class my_reg_callback extends uvm_reg_cbs; function new(string name = "my_reg_callback"); super.new(name); endfunction virtual function void pre_read(uvm_reg rg); // Perform pre-read tasks endfunction virtual function void post_read(uvm_reg rg); // Perform post-read tasks endfunction virtual function void pre_write(uvm_reg rg); // Perform pre-write tasks endfunction virtual function void post_write(uvm_reg rg); // Perform post-write tasks endfunction endclass // Register the callback with the desired register block my_reg_callback reg_cb = new(); my_register_block.my_register.add_callback(reg_cb); ``` In this example, `my_reg_callback` is a user-defined class derived from `uvm_reg_cbs`. It defines the callback methods `pre_read`, `post_read`, `pre_write`, and `post_write` which will be called by UVM framework at corresponding events. The callback object `reg_cb` is created and added to the desired register block using the `add_callback` method. This will enable the callback functionality for the specific register block. Please note that this is just a basic example, and there are more advanced features and options available for UVM register callbacks. The UVM User Guide provides detailed information on using and customizing register callbacks.
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