8b10b_encode

//#########################################################################//
//              Data        :   2023/12/2
//              origin      :   Xilinx
//              modified by :   jiayu Chen
//              PJ Name     :   xxxx
//              Model Name  :   xxxx
//              Version     :   1.0
//              Describle   : 
//              E-mail      : cjy18816252779@163.com
//########################################################################//
`timescale	1ps/1ps

module encode_8b10b (
    input                               clk                                     ,

    input       [7:0]                   data_in8b                               ,
    output      [9:0]                   data_out10b                 
);
	
	// -------------------------------------------------------------
	// Internal	signal definition
	// -------------------------------------------------------------
    reg         [3:0]                   r_n1d                                   = 4'd0;// 1 number 
    reg         [7:0]                   r_data_in8b                             = 8'd0;
    wire        [8:0]                   s_q_m                                   ;
    reg         [8:0]                   r_q_m_0dff                              = 9'd0 ;

    wire                                s_judge1                                ;
    reg         [5:0]                   r_cnt                                   = 6'd0 ;      
    reg         [3:0]                   r_q_m_n1                                = 4'd0 ;
    reg         [3:0]                   r_q_m_n0                                = 4'd0 ;  
   
    reg         [9:0]                   r_q_out                                 = 10'd0 ;

    wire                                s_judge2                                ;
    wire                                s_judge3                                ;


// =============================================================================    
// RTL Body
// =============================================================================
    // data sync and sum 1 number
    always @( posedge clk ) begin
        r_n1d       <= data_in8b[7] + data_in8b[6] + data_in8b[5] + data_in8b[4] +
                       data_in8b[3] + data_in8b[2] + data_in8b[1] + data_in8b[0] ;
        r_data_in8b <= data_in8b ;
    end
	// -------------------------------------------------------------
	// judge1
	// -------------------------------------------------------------
    assign      s_judge1                = ( r_n1d > 4'd4 ) | ((r_n1d == 4'd4) && (r_data_in8b[0] == 1'b0 ))    ;

    assign      s_q_m[0]                = r_data_in8b[0] ;
    assign      s_q_m[1]                = s_judge1 ? ~(s_q_m[0] ^ r_data_in8b[1]) :( s_q_m[0] ^ r_data_in8b[1]) ;
    assign      s_q_m[2]                = s_judge1 ? ~(s_q_m[1] ^ r_data_in8b[2]) :( s_q_m[1] ^ r_data_in8b[2]) ;
    assign      s_q_m[3]                = s_judge1 ? ~(s_q_m[2] ^ r_data_in8b[3]) :( s_q_m[2] ^ r_data_in8b[3]) ;
    assign      s_q_m[4]                = s_judge1 ? ~(s_q_m[3] ^ r_data_in8b[4]) :( s_q_m[3] ^ r_data_in8b[4]) ;
    assign      s_q_m[5]                = s_judge1 ? ~(s_q_m[4] ^ r_data_in8b[5]) :( s_q_m[4] ^ r_data_in8b[5]) ;
    assign      s_q_m[6]                = s_judge1 ? ~(s_q_m[5] ^ r_data_in8b[6]) :( s_q_m[5] ^ r_data_in8b[6]) ;
    assign      s_q_m[7]                = s_judge1 ? ~(s_q_m[6] ^ r_data_in8b[7]) :( s_q_m[6] ^ r_data_in8b[7]) ;
    assign      s_q_m[8]                = s_judge1 ? 0                            :  1                          ;
	// -------------------------------------------------------------
	// judge2
	// -------------------------------------------------------------
    // sum s_q_m 1 & 0 number   sync s_q_m
    always @( posedge clk ) begin
        r_q_m_n1 <= s_q_m[0] + s_q_m[1] + s_q_m[2] + s_q_m[3] + s_q_m[4] + 
                    s_q_m[5] + s_q_m[6] + s_q_m[7] ;
        r_q_m_n0 <= 4'd8 - s_q_m[0] - s_q_m[1] - s_q_m[2] - s_q_m[3] - s_q_m[4] -
                    s_q_m[5] - s_q_m[6] - s_q_m[7] ;
    end

    always @( posedge clk ) begin
        r_q_m_0dff <= s_q_m ;
    end

    assign      s_judge2                = ( r_cnt == 6'd0 ) | ( r_q_m_n1 == r_q_m_n0 ) ;
    assign      s_judge3                = (( ~r_cnt[5] ) && ( r_q_m_n1 > r_q_m_n0 )) | ( r_cnt[5] && ( r_q_m_n1 < r_q_m_n0 )) ;

	// -------------------------------------------------------------
	// output
	// -------------------------------------------------------------

    always @( posedge clk ) begin
        if ( s_judge2 == 1'b1 ) begin
            r_q_out[9]      <= ~r_q_m_0dff[8] ;
            r_q_out[8]      <=  r_q_m_0dff[8] ;
            r_q_out[7:0]    <=  r_q_m_0dff[8] ? r_q_m_0dff[7:0] : ~r_q_m_0dff[7:0] ;
            r_cnt           <=  r_q_m_0dff[8] ? ( r_cnt + r_q_m_n1 - r_q_m_n0 ) : ( r_cnt +  r_q_m_n0 - r_q_m_n1 ) ;
        end else begin
            if ( s_judge3 == 1'b1 ) begin
                r_q_out[9]      <= 1 ;
                r_q_out[8]      <= r_q_m_0dff[8] ;
                r_q_out[7:0]    <=~r_q_m_0dff[7:0] ;
                r_cnt           <= r_cnt + {r_q_m_0dff[8],1'b0} + r_q_m_n0 - r_q_m_n1  ;     
            end else begin
                r_q_out[9]      <= 0 ;
                r_q_out[8]      <= r_q_m_0dff[8] ;
                r_q_out[7:0]    <= r_q_m_0dff[7:0] ;
                r_cnt           <= r_cnt - {~r_q_m_0dff[8],1'b0} + r_q_m_n1 - r_q_m_n0 ;                 
            end
        end
    end


    assign      data_out10b             = r_q_out ;




    
endmodule