8b10b_decode

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已于 2024-01-16 23:37:21 修改

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分类专栏：编解码文章标签： fpga开发

于 2024-01-16 23:23:48 首次发布

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//#########################################################################//
//              Data        :   2023/12/2
//              origin      :   Xilinx
//              modified by :   jiayu Chen
//              PJ Name     :   xxxx
//              Model Name  :   xxxx
//              Version     :   1.0
//              Describle   : 
//              E-mail      : cjy18816252779@163.com
//########################################################################//
//========================================================================//
//	RTL Header
//========================================================================//
`timescale	1ps/1ps
module decode_8b10b (
    input                               clk                                     ,
    input       [9:0]                   data_in10b                              ,
    output      [7:0]                   data_out8b                              
);
    //------------------------------------------------------------------------//
    //	Defination	of	Internal	Signals
    //------------------------------------------------------------------------//
    wire        [7:0]                   s_data_in10b_8b                         ;
    reg         [7:0]                   r_data_out8b                            = 8'd0 ;

//========================================================================//
//	RTL	Body	
//========================================================================//

    assign      s_data_in10b_8b         =~data_in10b[7:0]                       ;

    always @( posedge clk ) begin
        case( data_in10b[9:8] )
            2'b11 :begin
                r_data_out8b[0] <= s_data_in10b_8b[0] ;
                r_data_out8b[1] <= s_data_in10b_8b[1] ^ s_data_in10b_8b[0] ;
                r_data_out8b[2] <= s_data_in10b_8b[2] ^ s_data_in10b_8b[1] ;
                r_data_out8b[3] <= s_data_in10b_8b[3] ^ s_data_in10b_8b[2] ;
                r_data_out8b[4] <= s_data_in10b_8b[4] ^ s_data_in10b_8b[3] ;
                r_data_out8b[5] <= s_data_in10b_8b[5] ^ s_data_in10b_8b[4] ;
                r_data_out8b[6] <= s_data_in10b_8b[6] ^ s_data_in10b_8b[5] ;
                r_data_out8b[7] <= s_data_in10b_8b[7] ^ s_data_in10b_8b[6] ;
            end
            2'b10 :begin
                r_data_out8b[0] <= s_data_in10b_8b[0] ;
                r_data_out8b[1] <=~s_data_in10b_8b[1] ^ s_data_in10b_8b[0] ;
                r_data_out8b[2] <=~s_data_in10b_8b[2] ^ s_data_in10b_8b[1] ;
                r_data_out8b[3] <=~s_data_in10b_8b[3] ^ s_data_in10b_8b[2] ;
                r_data_out8b[4] <=~s_data_in10b_8b[4] ^ s_data_in10b_8b[3] ;
                r_data_out8b[5] <=~s_data_in10b_8b[5] ^ s_data_in10b_8b[4] ;
                r_data_out8b[6] <=~s_data_in10b_8b[6] ^ s_data_in10b_8b[5] ;
                r_data_out8b[7] <=~s_data_in10b_8b[7] ^ s_data_in10b_8b[6] ;
            end
            2'b01 :begin
                r_data_out8b[0] <= data_in10b[0] ;
                r_data_out8b[1] <= data_in10b[1] ^ data_in10b[0] ;
                r_data_out8b[2] <= data_in10b[2] ^ data_in10b[1] ;
                r_data_out8b[3] <= data_in10b[3] ^ data_in10b[2] ;
                r_data_out8b[4] <= data_in10b[4] ^ data_in10b[3] ;
                r_data_out8b[5] <= data_in10b[5] ^ data_in10b[4] ;
                r_data_out8b[6] <= data_in10b[6] ^ data_in10b[5] ;
                r_data_out8b[7] <= data_in10b[7] ^ data_in10b[6] ;
            end
            2'b00 :begin
                r_data_out8b[0] <= data_in10b[0] ;
                r_data_out8b[1] <=~data_in10b[1] ^ data_in10b[0] ;
                r_data_out8b[2] <=~data_in10b[2] ^ data_in10b[1] ;
                r_data_out8b[3] <=~data_in10b[3] ^ data_in10b[2] ;
                r_data_out8b[4] <=~data_in10b[4] ^ data_in10b[3] ;
                r_data_out8b[5] <=~data_in10b[5] ^ data_in10b[4] ;
                r_data_out8b[6] <=~data_in10b[6] ^ data_in10b[5] ;
                r_data_out8b[7] <=~data_in10b[7] ^ data_in10b[6] ;
            end
            default: ;
        endcase
    end

    assign      data_out8b = r_data_out8b ;

endmodule