三段式状态机VGA显示程序及仿真

三段式状态机VGA显示程序及仿真
module vgas(iclk,oclk,rst,valid_r,sync,datacolor,H_sync,V_sync);

input iclk,rst;

output oclk;

output valid_r;

output sync;

output [23:0]datacolor;

output H_sync;

output V_sync;

reg [15:0] hcount=0;

reg [15:0] vcount=0;

reg [3:0] hstate;

reg [3:0] vstate;

reg [3:0] h_nextstate;

reg [3:0] v_nextstate;

reg H_sync;

reg V_sync;

//reg valid;

reg [23:0] color;

reg [7:0] R;

reg [7:0] G;

reg [7:0] B;

wire [23:0] datacolor;

wire valid_r;

parameter a=4’b1000,

      b=4'b0100,

c=4’b0010,

d=4’b0001,

h=4’b1000,

      i=4'b0100,

j=4’b0010,

k=4’b0001;

always@(posedge clk )

begin

if(hcount==16’d799)

hcount<=0;

else

hcount<=hcount+1;

end

//列计数

always@(posedge clk )

 begin

if((vcount==16’d524)&&(hcount==16’d799))

vcount<=0;

else if(hcount==16’d799)

vcount<=vcount+1;

 end

//行状态迁移

always @(posedge clk) begin

if(!rst)

hstate<=a;

else

hstate<=h_nextstate;

end

always @(*) begin

   h_nextstate=a;

case(hstate)

a: begin

if(hcount>95)

h_nextstate=b;

else

h_nextstate=a;

end

b: begin

if(hcount>142)

h_nextstate=c;

else

h_nextstate=b;

end

c: begin

if(hcount>782)

h_nextstate=d;

else

h_nextstate=c;

end

d: begin

if(hcount>798)

h_nextstate=a;

else

h_nextstate=d;

end

default:h_nextstate=a;

endcase

end

///描述次态寄存器输出

always @(posedge clk) begin

case(h_nextstate)

a: H_sync<=0;

b: H_sync<=1;

c: H_sync<=1;

     d: H_sync<=1;

    default:H_sync<=h;

endcase

end

//场状态迁移

always @(posedge clk) begin

if(!rst)

vstate<=h;

else

vstate<=v_nextstate;

end

always @(*) begin

   v_nextstate=h;

case(vstate)

h: begin

if(vcount>0)

v_nextstate=i;

else

v_nextstate=h;

end

i: begin

if(vcount>33)

v_nextstate=j;

else

v_nextstate=i;

end

j: begin

if(vcount>513)

v_nextstate=k;

else

v_nextstate=j;

end

k: begin

if(vcount>523)

v_nextstate=h;

else

v_nextstate=k;

end

default:v_nextstate=h;

endcase

end

//

always @(posedge clk) begin

case(v_nextstate)

h: V_sync<=0;

i: V_sync<=1;

j: V_sync<=1;

     k: V_sync<=1;

    default:V_sync<=0;

endcase

end

assign valid_r=H_sync&V_sync;

always @(posedge clk) begin

if(valid_r)

begin

if((hcount>143)&&(hcount<=223)) color<=24’h111111;

if((hcount>223)&&(hcount<=303)) color<=24’h101111;

if((hcount>303)&&(hcount<=383)) color<=24’h110111;

if((hcount>383)&&(hcount<=463)) color<=24’h111100;

if((hcount>463)&&(hcount<=543)) color<=24’h111110;

if((hcount>543)&&(hcount<=623)) color<=24’h011101;

if((hcount>623)&&(hcount<=703)) color<=24’h110011;

if((hcount>703)&&(hcount<=783)) color<=24’h111100;

end

else color<=24’h000000;

end

assign datacolor=color;

assign sync=1;

vgascore instance_name

(// Clock in ports

.CLK_IN1(iclk),      // IN

// Clock out ports

.CLK_OUT1(clk),     // OUT

.CLK_OUT2(CLK_OUT_NON));    // OUT

// INST_TAG_END —— End INSTANTIATION Template ———

ODDR2 #(

  .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 

  .INIT(1'b0),    // Sets initial state of the Q output to 1'b0 or 1'b1

  .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset

)

ODDR2_inst (

  .Q(oclk),   // 1-bit DDR output data

  .C0(CLK_OUT_NON),   // 1-bit clock input

  .C1(~CLK_OUT_NON),   // 1-bit clock input

  .CE(1'b1), // 1-bit clock enable input

  .D0(1'b1), // 1-bit data input (associated with C0)

  .D1(1'b0), // 1-bit data input (associated with C1)

  .R(1'b0),   // 1-bit reset input

  .S(1'b0)    // 1-bit set input

);

// End of ODDR2_inst instantiation

endmodule

仿真程序如下：

module vgatesttwo;

// Inputs

reg iclk;

reg rst;

// Outputs

wire oclk;

wire valid_r;

wire sync;

wire [23:0] datacolor;

wire H_sync;

wire V_sync;

// Instantiate the Unit Under Test (UUT)

vgas uut (

.iclk(iclk),

.oclk(oclk),

.rst(rst),

.valid_r(valid_r),

.sync(sync),

.datacolor(datacolor),

.H_sync(H_sync),

.V_sync(V_sync)

);

initial begin

// Initialize Inputs

iclk = 0;

rst = 0;

// Wait 100 ns for global reset to finish

100;

// Add stimulus here

 #5 rst=1;

end

 always 

#5 iclk<=!iclk;

endmodule