Fsm serialdp

Fsm serialdp
HDLBIT

原文对问题得描述也有些问题。
之前写的状态机不怎么规范，重新去看了看状态机的规范。**

时序电路用周期内稳定的next_state做判断，组合逻辑用周期内稳定的current_state做判断。

**
如果你够牛你可以在时序电路中用current_state。

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
parameter IDLE=4'd0,START=4'd1,RXD=4'd2,STOP=4'd3,WAIT=4'd4,PARITY=4'd5;
    reg [7:0] out_byte_reg;
    reg [3:0] current_state;
    reg [3:0] next_state;
    wire odd;
    wire re;
    reg [3:0] cnt_byte;
    always @(posedge clk)
        begin
            if(reset)
                current_state<=IDLE;
            else
                current_state<=next_state;
        end
    always @(*) begin
        case(current_state)
        IDLE:next_state=(in==0)?START:IDLE;
        START:next_state=RXD;
        RXD:next_state=(cnt_byte==8)?PARITY:RXD;
        PARITY:next_state=(in==1)?STOP:WAIT;
        STOP:next_state=(in==0)?START:IDLE;
        WAIT:next_state=(in==1)?IDLE:WAIT;
        default:next_state=IDLE;
        endcase
    end
    
    always @(posedge clk) begin
        if(reset)
            cnt_byte<=0;
        else if(next_state==RXD)
            begin
                out_byte_reg[cnt_byte]<=in;
                cnt_byte<=cnt_byte+1;
            end
        else 
            cnt_byte<=0;
    end
    
    parity u1(
        .clk(clk),
        .reset(reset || next_state == IDLE || next_state == START),
        .in(in),
        .odd(odd)
    );
    assign done=((current_state == STOP)&&(~odd));
    assign out_byte=done?out_byte_reg:8'bz;
    /*always @(posedge clk) begin
        if(current_state==STOP&&done==1)
            out_byte<=out_byte_reg;
        else
            out_byte<=8'bz;
            
    end*/
    // Modify FSM and datapath from Fsm_serialdata

    // New: Add parity checking.

endmodule