SOC课程——⑧——根据状态图FSM,写出system_verilog代码

题目：

module

module sv03_fsm(A,B,clk,Reset,Y);
input logic A,B,clk,Reset;
output logic Y;

enum logic[1:0]{S0=2'b00,S1=2'b01,S2=2'b10,S3=2'b11}curr_s,next_s;

always_ff@(posedge clk,negedge Reset)begin
if(Reset == 1'b0)curr_s <= S0;
else curr_s<= next_s;
end

always_comb begin
case(curr_s)
	S0:	if(A^B) next_s<=S1;
		else 	next_s<=S0;
	S1:	if(A&B) next_s<=S2;
		else if(~(A&B)) next_s<=S1;
	S2:	if(A|B) next_s<=S3;
		else if(~(A|B)) next_s<=S0;
	S3:	if(A|B) next_s<=S3;
		else if(~(A|B))next_s<=S0;
endcase
end

always_comb begin
	if(curr_s == S0) Y<=0;
	else if(curr_s == S3)Y<=0;
	else if(curr_s == S1)Y<=1;
	else if(curr_s == S2)Y<=1;
end
endmodule

testbench

module sv03_fsm_tb();
logic A,B;
logic clk=0;
logic Reset;

always #5 clk = ~clk;

sv03_fsm sv03(.A(A),.B(B),
	.clk(clk),.Reset(Reset),.Y(Y));

initial begin
A=0;
B=0;
Reset = 1;
#5 Reset=0;
#8 Reset=1;
end

always #4 A={$random}%2;
always #4 B={$random}%2;

endmodule

仿真结果：