#************parameter input*************
#※prepare the source list file and then make add the soucefile name
#for example ,the Verilog source file's name is vlog_list.f then :make norsim src_list=file_list
src_list = filelist
simv_name = simv_yolo
vpdpluse_name = vcdpluse_yolo
cov_file_name = coverage
vdb_name = $(simv_name)
ALL_DEFINE = +define+DUMP_VPD
#************constant command************
#compile
NOR_VCS = vcs -full64 -sverilog +v2k -timescale=1ns/1ns \
-debug_all \
-debug_pp \
+notimingcheck \
+nospecify \
+incdir+./../rtl/ \
+vcs+flush+all \
-o $(simv_name) \
-l compile.log \
-f $(src_list).f
#coverage compile switch
COV_SW = -cm line+cond+fsm+branch+tgl
#verdi dump wave compile option
VERDI_SW = -P /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas.tab \
/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a
#run option
RUN_GUI = -R -gui -l run.log
RUN_VPD = -R +vpdfile+$(vpdpluse_name).vpd -l run.log
RUN_COV = -R $(COV_SW) -cm_name $(vdb_name) -cm_dir ./$(cov_file_name) -l run.log
RUN_VER = -R +fsdb+autoflush -l run.log
MYRUN_VPD = +vpdfile+$(vpdpluse_name).vpd
#************command************
#mycommand: comsim
comsim:
$(NOR_VCS) $(ALL_DEFINE) $(MYRUN_VPD)
./$(simv_name) $(MYRUN_VPD) -l $(simv_name).log
#mycommand: debug
debug:
dve -vpd $(vpdpluse_name).vpd &
#mycommand: myorder
myorder:
$(NOR_VCS) $(ALL_DEFINE) $(MYRUN_VPD) +memcbk
./$(simv_name) $(MYRUN_VPD) -l $(simv_name).log
dve -vpd $(vpdpluse_name).vpd &
#normally sim
norsim:
$(NOR_VCS) $(RUN_GUI)
#post-process
postsim:
$(NOR_VCS) $(RUN_VPD)
dve -vpd $(vpdpluse_name).vpd
#coverage
covsim:
$(NOR_VCS) $(COV_SW) $(RUN_COV)
dve -covdir $(cov_file_name).vdb
#verdi
versim:
$(NOR_VCS) $(VERDI_SW) $(RUN_VER)
verdi -sv -f $(src_list).f -ssf *.fsdb -nologo &
#rm
clr:
rm -rf *csrc ./*.daidir $(simv_name) *simv* DVE* ucli* *.vpd *.vdb *.log *.fsdb *novas* *.dat *Log *rc *conf
用VCS仿真硬件电路中MAKEFILE文件的编写
最新推荐文章于 2024-01-23 16:12:59 发布