Verilog :Fsm3comb/onehot/异步复位/同步复位

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已于 2024-03-25 17:08:47 修改

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分类专栏： HDLBits-一起刷题呀文章标签： fpga开发

于 2024-03-25 16:59:43 首次发布

本文链接：https://blog.csdn.net/weixin_46439180/article/details/137018926

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Fsm3comb - HDLBits (01xz.net)https://hdlbits.01xz.net/wiki/Fsm3comb

代码：

module top_module(
    input in,
    input [1:0] state,
    output [1:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: next_state = f(state, in)
	always @(*) begin
        case(state)
            A: next_state = in ? B : A;
            B: next_state = in ? B : C;
            C: next_state = in ? D : A;
            D: next_state = in ? B : C;
        endcase
    end
    // Output logic:  out = f(state) for a Moore state machine
    assign out = (state == D)?1:0;

endmodule

onehot代码：

module top_module(
    input in,
    input [3:0] state,
    output [3:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] = (state[A]&&(~in))|(state[C]&&(~in));
    assign next_state[B] = (state[A]&&in)|(state[B]&&in)|(state[D]&&in);
    assign next_state[C] = (state[B]&&(~in))|(state[D]&&(~in));
    assign next_state[D] = state[C]&&in;

    // Output logic: 
    assign out = state[D];

endmodule

异步复位代码：

module top_module(
    input clk,
    input in,
    input areset,
    output out); //
    reg [1:0] state;
    reg [1:0] next_state;
    parameter A=0, B=1, C=2, D=3;
    // State transition logic
	always @(*) begin
        case(state)
            A: next_state = in ? B : A;
            B: next_state = in ? B : C;
            C: next_state = in ? D : A;
            D: next_state = in ? B : C;
        endcase
    end
    // State flip-flops with asynchronous reset
    always @(posedge clk or posedge areset) begin
        if(areset)
            state<=A;
        else state<=next_state;
    end
    // Output logic
    assign out = (state == D)?1:0;
endmodule

同步复位：

module top_module(
    input clk,
    input in,
    input reset,
    output out); //
    reg [1:0] state;
    reg [1:0] next_state;
    parameter A=0, B=1, C=2, D=3;
    // State transition logic
	always @(*) begin
        case(state)
            A: next_state = in ? B : A;
            B: next_state = in ? B : C;
            C: next_state = in ? D : A;
            D: next_state = in ? B : C;
        endcase
    end
    // State flip-flops with asynchronous reset
    always @(posedge clk) begin
        if(reset)
            state<=A;
        else state<=next_state;
    end
    // Output logic
    assign out = (state == D)?1:0;
endmodule