2021-06-26

1.实验目的：
（1）掌握有限状态机的写法
（2）理解三段式与两段式的写法与区别
2.实验内容：
完成一个序列信号检测器。
3.实验代码：
module s7(x,z,clk,reset);
input x,clk,reset;
output z;
reg z;
reg[2:0] state,nstate;
parameter s0='d0,s1='d1,s2='d2,s3='d3,s4='d4,s5='d5;

always @(posedge clk or posedge reset)
begin
if(reset)
state<=s0;
else
state<=nstate;
end

endmodule
改进后：
module s7(x,z,clk,reset);
input x,clk,reset;
output z;
reg z;
reg[2:0] state,nstate;

parameter s0='d0,s1='d1,s2='d2,s3='d3,s4='d4,s5='d5;

always @(posedge clk or posedge reset)
begin
if(reset)
state<=s0;
else
state<=nstate;
end

always@(state or x)
begin
casex(state)
s0: begin
if(x1)
nstate=s1;
else
nstate=s0;
end
s1: begin
if(x0)
nstate=s2;
else
nstate=s1;
end
s2: begin
if(x0)
nstate=s3;
else
nstate=s1;
end
s3: begin
if(x0)
nstate=s4;
else
nstate=s1;
end
s4: begin
if(x0)
nstate=s5;
else
nstate=s1;
end
s5: begin
if(x0)
nstate=s0;
else
nstate=s1;
end
default: nstate=s0;
endcase
end

always@(posedge clk)
begin
casex(nstate)
s0: z<=0;
s1: z<=0;
s2: z<=0；
s3: z<=0;
s4: z<=0;
s5: z<=1;
default: z<=0;
endcase
end

endmodule
测试模块：
module tbs7;
reg x,clk,reset;
wire z;
integer seed=9;

initial clk=0;
always #5 clk=~clk;

initial
begin
reset=0;
#15 reset=1;
#15 reset=0;
end

always
#10 x={$random(seed)}%2;

s7 mys7(x,z,clk,reset);

endmodule
顶层设计代码修改
module seq(data,reset,clock,z,look1,look2);
input [9:0] data;
input clock,reset;
output z,look1,look2;

wire clk,x;

div mydiv(clook,reset,clk);
chs mychs(data,clk,reset,x);
s7 mys7(x,z,clk,reset);

assign look1=clk;
assign lookk2=x;

endmodule

module div(clk_in,reset,clk_out);
input clk_in,reset;
output clk_out;
reg clk_out;
reg [29:0] count;

always @(posedge clk_in)
if(reset)
count<=0;
else if(count==30’d24999999)
count<=0;
else
count<=count+1;

always @(posedge clk_in)
if(reset)
clk_out<=0;
else if(count==30’d24999999)
clk_out<=~clk_out;
else
clk_out<=clk_out;

endmodule

module chs(data,clk,reset,x);
input [9:0] data;
input clk,reset;
output x;

reg [9:0] count;

always @(posedge clk)
if(reset)
count<=0;
else if(count<9)
count<=count+1;
else
count<=0;

assign x=data[count];

endmodule
4.实验截图：


5.实验工具：
modulsim
6.实验视频：
请下载哔哩哔哩动画打开此网址：【有限状态机的设计-哔哩哔哩】https://b23.tv/jq0GcC
【有限状态机-哔哩哔哩】https://b23.tv/Ebiu4M