阻塞赋值与非阻塞赋值所带来的差异比较巨大,所以要谨慎使用,官方推荐的写法是在组合逻辑电路中使用阻塞赋值,而在时序逻辑电路中使用非阻塞赋值
module blocking ( input wire clk, input wire res_n, input wire [1:0] in, output reg [1:0] out ); reg in_reg; always@(posedge clk or negedge res_n) if(res_n == 1'b0) begin in_reg = 2'b0; out = 2'b0; end else begin in_reg = in; out = in_reg; end endmodule
`timescale 1ns/1ns module tb_blocking(); reg clk; reg res_n; reg [1:0] in; wire [1:0] out; initial begin clk = 1'b1; res_n <= 1'b0; in <= 2'b0; #20 res_n <= 1'b1; end always #10 clk = ~clk; always #20 in <= {$random} % 4; blocking blocking_1 ( .clk(clk), .res_n(res_n), .in(in), .out(out) ); endmodule
module blocking ( input wire clk, input wire res_n, input wire [1:0] in, output reg [1:0] out ); reg in_reg; always@(posedge clk or negedge res_n) if(res_n == 1'b0) begin in_reg <= 2'b0; out <= 2'b0; end else begin in_reg <= in; out <= in_reg; end endmodule
FPGA学习笔记 -- 阻塞赋值与非阻塞赋值
最新推荐文章于 2024-04-29 05:37:31 发布