设计目标
(1)认识ROM
(2) 用计数器生成地址、读取ROM数据
(3) 用SignalTAP观察ROM的输出波形
(4) 理解二进制补码和无符号数
(5) 修改计数增量值,观察波形变化,思考输出频率 和计数器增量值的关系。
// ************************************************************** //
// FILE : sine_rom.v
// DSCP : sine_rom FILE
// ABOUT : auto generated rom file by gen_rom_rtl.m
// DATE : 14-Nov-2013 16:29:45
// ************************************************************** //
// module sine_rom()
module sine_rom(
CLK , // clock
RA , // read address
RD ); // read data
input CLK;
input [6 :0] RA;
output [7 :0] RD;
reg [7 :0] RD;
always @ (posedge CLK)
case(RA)
7 'd 0 :RD = #1 8 'b 00000000; // 0 0x0
7 'd 1 :RD = #1 8 'b 00000110; // 6 0x6
7 'd 2 :RD = #1 8 'b 00001100; // 12 0xC
7 'd 3 :RD = #1 8 'b 00010010; // 18 0x12
7 'd 4 :RD = #1 8 'b 00011000; // 24 0x18
7 'd 5 :RD = #1 8 'b 00011110; // 30 0x1E
7 'd 6 :RD = #1 8 'b 00100100; // 36 0x24
7 'd 7 :RD = #1 8 'b 00101010; // 42 0x2A
7 'd 8 :RD = #1 8 'b 00110000; // 48 0x30
7 'd 9 :RD = #1 8 'b 00110110; // 54 0x36
7 'd 10 :RD = #1 8 'b 00111011; // 59 0x3B
7 'd 11 :RD = #1 8 'b 01000001; // 65 0x41
7 'd 12 :RD = #1 8 'b 01000110; // 70 0x46
7 'd 13 :RD = #1 8 'b 01001011; // 75 0x4B
7 'd 14 :RD = #1 8 'b 01010000; // 80 0x50
7 'd 15 :RD = #1 8 'b 01010101; // 85 0x55
7 'd 16 :RD = #1 8 'b 01011001; // 89 0x59
7 'd 17 :RD = #1 8 'b 01011110; // 94 0x5E
7 'd 18 :RD = #1 8 'b 01100010; // 98 0x62
7 'd 19 :RD = #1 8 'b 01100110; // 102 0x66
7 'd 20 :RD = #1 8 'b 01101001; // 105 0x69
7 'd 21 :RD = #1 8 'b 01101100; // 108 0x6C
7 'd 22</