实验三：计数器、波形仿真、SignalTap

0-9计数器

module cnt_0to9(clk,ov);
input clk;
output ov;
reg ov;
reg [27:0] con;
always@(posedge clk)
    begin
        if(con==50000000)
        begin
            ov<=1;
            con<=0;
        end
        else
        begin
        ov<=0;
        con<=con+1;
        end
    end
endmodule

module cnt_1to9(CNTVAL,nv,clk1);
input clk1;
output [3:0]CNTVAL;
reg [3:0]CNTVAL;
output nv;
reg nv;
reg [3:0]count;
always@(posedge clk1)
    begin
            if(count==9)
            begin
            nv=1;
            end
            else
            begin
            count=count+1;
            nv=0;
            end
        CNTVAL=count;
    end
endmodule

    module yima(in,out);
input[3:0] in;
output[7:0] out;
reg[7:0] out;
always@(in)
    begin
        case(in)
            4'b0000:out=8'b11000000;
            4'b0001:out=8'b11111001;
            4'b0010:out=8'b10100100</