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RSS订阅翻译 Art of Writing TestBenches（of verilog HDL） Part - IV
Adding compare Logic //添加比较逻辑 To make any testbench self checking/automated, first we need to develop a model that mimics the DUT in functionality. 为了是测试基准程序能偶自动校验，我首先要开发一个模型能够反应DuT的功能。
2012-11-27 21:43:01
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翻译 Art of Writing TestBenches Part - III
Adding Reset Logic Once we have the basic logic to allow us to see what our testbench is doing, we can next add the reset logic. 我们一旦有基本逻辑时我们能够看清楚我们的测试基准程序在做什么，我们可以添加reset逻辑了。If we lo
2012-11-27 21:37:58
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翻译 Art of Writing TestBenches （of Verilog HDL） Part - II
Writing a TestBench //写一个测试用例 First step of any testbench creation is building a dummy template which basically declares inputs to DUT as reg and outputs from DUT as wire, then instantia
2012-11-27 21:25:17
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翻译 Art of Writing TestBenches （of Verilog HDL） Part - I
Introduction //简介 Writing a testbench is as complex as writing the RTL code itself. These days ASICs are getting more and more complex and thus verifying these complex ASIC has become a c
2012-11-27 20:50:33
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翻译 Art of Writing TestBenches (of Verilog HDL)
Introduction //简介 Before you Start Example - Counter 计数器举例 Code for CounterTest PlanTest Cases
2012-11-27 20:21:15
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翻译 System Task and Function (of Verilog HDL)
Introduction //简介 $display, $strobe, $monitor Syntax$time, $stime, $realtime$reset, $stop, $finish$scope, $showscope$ra
2012-11-27 20:16:53
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翻译 Task And Function （of Verilog HDL)
Task //任务（task） Syntax //语法Example - Simple Task // 简单的任务举例Example - Task using Global Variables //使用全局变量的任务Calling a Task //调用一个任务Example - CPU Wr
2012-11-27 19:18:29
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翻译 Procedural Timing Control （of Verilog HDL）
Procedural blocks and timing controls. //过程块和时间控制 Delay Controls //时间延迟控制 Example - clk_genWaveformEdge sensitive Event Controls 边沿触发的事件控
2012-11-27 17:03:15
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翻译 Verilog HDL Behavioral Modeling Part-V
Procedural Block Control //过程块的控制 Procedural blocks become active at simulation time zero. Use level sensitive event controls to control the execution of a procedure.过程块在仿真时刻0开始执行。使用电平触
2012-11-27 16:37:39
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翻译 Verilog HDL Behavioral Modeling Part-IV
Continuous Assignment Statements //连续赋值语句 Continuous assignment statements drive nets (wire data type). They represent structural connections.连续赋值语句能够驱动线网类型（net类型 如wire). 它们用来表示结构化的连接。
2012-11-27 15:12:58
874
翻译 Verilog HDL Behavioral Modeling Part-III
Looping Statements // 循环语句 Looping statements appear inside procedural blocks only; Verilog has four looping statements like any other programming language.循环语句只出现在过程块内。 Verilog HDL与其他编
2012-11-27 14:59:33
698
翻译 Verilog HDL Behavioral Modeling Part-II
The Conditional Statement if-else //if-else 条件语句 The if - else statement controls the execution of other statements. In programming language like c, if - else controls the flow of program
2012-11-27 12:39:26
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翻译 Verilog HDL Behavioral Modeling Part-I
Verilog HDL Abstraction Levels //Verilog HDL 的抽象层次 Behavioral Models : Higher level of modeling where behavior of logic is modeled. //行为建模：为逻辑行为建模的高级建模RTL Models : Logic
2012-11-27 11:15:23
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翻译 Verilog HDL Behavioral Modeling (Verilog HDL 行为建模）
Verilog HDL Abstraction Levels //Verilog HDL 抽象层次 Procedural Blocks //过程块 Example - initial //initial块举例Example - always //always 块举例Pr
2012-11-27 09:57:15
1133
翻译 Verilog HDL Operators Part-II
Reduction Operators// 规约操作 OperatorDescription&and~&nand|or~|nor^xor
2012-11-23 17:06:23
1131
翻译 Verilog HDL Operators Part-I
Arithmetic Operators //算术操作符 Binary: +, -, *, /, % (the modulus operator) //二元操作符Unary: +, - (This is used to specify the sign) //单目操作符（指明符号位）Integer division truncates
2012-11-23 16:51:03
829
翻译 Verilog HDL Operators
Arithmetic Operators //算术操作符 Example Relational Operators //关系操作符 Example Equality Operat
2012-11-23 16:22:02
673
翻译 User Defined Primitives Part-III (of Verilog HDL)
Level Sensitive Sequential UDP //电平触发的时序udp Level-sensitive sequential behavior is represented in the same way as combinational behavior, except that the output is declared to be of type
2012-11-23 16:15:36
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翻译 User Defined Primitives Part-II (of Verilog HDL)
Combinational UDPs //组合逻辑 UDP In combinational UDPs, the output is determined as a function of the current input. Whenever an input changes value, the UDP is evaluated and one of the stat
2012-11-23 15:40:22
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翻译 User Defined Primitives Part-I (of Verilog HDL)
Introduction // 简介 Verilog has built-in primitives like gates, transmission gates, and switches. This is a rather small number of primitives; if we need more complex primitives, then Veri
2012-11-23 15:09:58
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翻译 User Defined Primitives ( of Verilog HDL)
Introduction //简介 Syntax //语法UDP ports rules //用户自定义原语的端口规则Body //主体 Table //真值表Initial //初始化Symbols //符号Combi
2012-11-23 13:13:09
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翻译 Gate Level Modeling Part-III (of Verilog HDL)
Gate and Switch delays //门时延和开关时延 In real circuits, logic gates have delays associated with them. Verilog provides the mechanism to associate delays with gates.在真正的电路中，逻辑电路都有一定的时延。Veril
2012-11-23 12:29:37
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翻译 Gate Level Modeling Part-II (of Verilog HDL)
Designing Using Primitives //使用门级原语的设计 Designing using primitives is used only in library development, where the ASIC vendor provides the ASIC library Verilog description, using Verilog p
2012-11-23 10:46:38
1127
翻译 Gate Level Modeling Part-I (of Verilog HDL)
Introduction Verilog has built in primitives like gates, transmission gates, and switches. These are rarely used in design (RTL Coding), but are used in post synthesis world for modeling
2012-11-23 10:33:29
2356
翻译 Gate Level Modeling (of Verilog HDL)
Gate Level Modeling (of Verilog HDL) Verilog HDL 的门级建模
2012-11-23 09:04:13
939
翻译 Verilog HDL Syntax And Semantics Part-III
Hierarchical Identifiers //层次型的标识符 Hierarchical path names are based on the top module identifier followed by module instant identifiers, separated by periods.层次性的路径名是上层模块的标识符后跟着模块标识符，使
2012-11-22 21:18:42
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翻译 Verilog HDL Syntax And Semantics Part-II
Modules //模块 Modules are the building blocks of Verilog designs //module 是Verilog中的构成blockYou create the design hierarchy by instantiating modules in other modules. //
2012-11-22 16:41:06
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翻译 Verilog HDL Syntax And Semantics Part-I
Lexical Conventions //词法约定The basic lexical conventions used by Verilog HDL are similar to those in the C programming language. Verilog HDL is a case-sensitive language. All keywords are in
2012-11-22 16:34:48
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翻译 Verilog HDL Syntax And Semantics
Lexical Conventions // 词法约定White Space //空格 Examples of White Spaces //空格举例Comments //注释 Examples of Comments // 注释举例
2012-11-22 14:45:15
782
翻译 My first program in Verilog HDL
Introduction //简介Hello World Program //Hello World 程序 Hello World Program Output //Hello World 程序的输出Counter Design Block /
2012-11-22 13:29:07
1366
翻译 Design And Tool Flow (of Verilog HDL)
Introduction //简介Various stages of ASIC/FPGA // ASIC（Application Specific Integrated Circuit ）/FPGA(Field Programming Gate Array) 设计的不同阶段Figure : Typical Design flo
2012-11-22 10:42:18
1642
翻译 History of Verilog HDL
History Of VerilogVerilog was started initially as a proprietary hardware modeling language by Gateway Design Automation Inc. around 1984. It is rumored that the original language was designed
2012-11-21 22:39:36
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翻译 Verilog HDL in one day Part-IV
Test Benches //测试基准 Ok, we have code written according to the design document, now what?好吧，我已经按照设计说明文档，编写了代码，现在做点什么呢？ Well we need to test it to see if it
2012-11-21 21:17:12
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翻译 Verilog HDL in one day Part-III
Always BlocksAs the name suggests, an always block executes always, unlike initial blocks which execute only once (at the beginning of simulation). A second difference is that an always block shou
2012-11-21 19:58:52
685
翻译 Verilog HDL in one Day Part-II
Control Statements // 控制语句Wait, what's this? if, else, repeat, while, for, case - it's Verilog that looks exactly like C (and probably whatever other language you're used to program in)! Eve
2012-11-21 16:29:23
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翻译 Verilog HDL In One Day Part-I
Introduction // 简介 Every new learner's dream is to understand Verilog in one day, at least enough to use it. The next few pages are my attempt to make this dream a reality. There will be
2012-11-21 15:29:34
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翻译 Verilog HDL In One Day (Verilog HDL 学习的第一天）
Introduction //简介Block diagram of arbiter //仲裁器的框图Low level design //底层设计Modules //模块Code of modu
2012-11-21 11:49:59
744
翻译 Introduction to Verilog （Verilog 简介）
Introduction to Verilog //Verilog简介Introduction //简介Bottom-Up Design //自底向上设计Top-Down Design //自顶向下设计Figur
2012-11-21 10:42:26
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翻译 Verilog Tutorial (Verilog 教程）
This Verilog tutorial was started a long time ago. Every time I update my web page, I make sure I add something new in the Verilog tutorial section. If you have been a frequent visitor, you should h
2012-11-21 09:27:24
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翻译 Welcome To Verilog (verilog 学习）
In this section you will find tutorial, examples, links, tools and books related to Verilog. Tutorials : This section contains a practical approach to Verilog. //教程
2012-11-21 09:03:27
750
Verilog HDL IEEE Std 1364-2001
2012-11-22
The Mathematics of the RSA Public-Key Cryptosystem
2012-01-05
RSA_theory ：RSA的数学原理
2012-01-05
stm32f10x_fw_archive.zip
2012-01-02
STM32F10X在Keil MDK环境下在RAM中调试的设置方法.pdf
2012-01-02
stm32f10x标准固件库的帮助文档（stm32f10x_stdperiph_lib_um.chm）
2012-01-02
MySQL中文参考手册-chm格式┊Mysql官方权威教程.rar
2008-12-03
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