Zynq的FPGA设计中[DRC 23-20]错误的解决

上次做DDS时出现了[DRC 23-20]，当时是这样处理的(并没有解决)：在网上搜了一下，新建一个tcl文件，在文件中添加

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]

set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1]

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

这几行语句，并在Project Settings中的Bitstream选项中添加新建的.tcl文本(tcl.pre栏)

怎么解决这个问题呢? 分析错误提示：

[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 3 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standa