Tb/tb2
The waveform below sets clk, in, and s:
Module q7 has the following declaration:
module q7 ( input clk, input in, input [2:0] s, output out );
Write a testbench that instantiates module q7 and generates these input signals exactly as shown in the waveform above.
module top_module();
reg clk;
reg in;
reg [2:0] s;
wire out;
q7 u_q7(
.clk(clk),
.in(in),
.s(s)
.out(out)
);
always #5 clk=~clk;
initial begin
clk=1'b0;
in=1'b0;
s=3'd2;
#10 s=3'd6;
#10 s=3'd2;
in=1'b1;
#10 s=3'd7;
in=1'b0;
#10 s=3'd0;
in=1'b1;
#30 in=1'b0;
end
endmodule