Which cell has lowest area among hvt, lvt and svt cells?

hvt , lvt and svt all have the same area. there is a single layout done and VT layer is used to generate the other versions. This helps the chip level tools to swap the cells of different VT to achieve the timing and power goals that are set.

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The cell area will be same irrespective of SVT/HVT/LVT.

The cell layout has many different layers, the difference between SVT & HVT cells are, VTH_P & VTH_N layers ( which are added in HVT Cells ), the difference between SVT & LVT cells are, VTL_P & VTl_N layers ( which are added in LVT Cells ).

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VT layer signifies the Fab people that the oxide layer should be thick.So depending on the Vt layer the silicon dioxide thickness below the poly is varied.

Vt variation can be done by changing oxide thickness, but in advanced scaled technology nodes, this is achieved by varying channel doping or changing the gate metal work function (for high-K metal gate transistors). While drawing the layouts in a layout editor (Virtuoso in Cadence, for example), you'd specify whether the transistor type is high/standard/low VT. Some technology nodes have a ULVT device as well, depends on the Fab offering the device options.
HVT will have a high threshold voltage, hence lower leakage and lower current drive. This directly translates to lower active/dynamic power. The converse is true for the LVT or the lowest VT transistor option available.

 

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