set_max_delay SDC

set_max_delay (SDC)

Specifies the maximum delay for the timing paths.

set_max_delay delay_value [-from from_list] [-to to_list]

Arguments

delay_value

Specifies a floating point number in nanoseconds that represents the required maximum delay value for specified paths.

1. If the ending point has an output delay specified, the tool adds that delay to the path delay.

2. If the path ending point is on a sequential device, the tool includes clock skew and library setup time in the computed delay.

3. If the path starting point has an input delay specified, the tool adds that delay value to the path delay.

4. If the path starting point is on a sequential device, the tool includes clock skew in the computed delay.

-from from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

 

-to to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

Supported Families

Fusion, ProASIC3/E, ProASICPLUS, Axcelerator, ProASIC (for analysis), eX (-through option), SX-A (-through option)

Description

This command specifies the required maximum delay for timing paths in the current design. The path length for any startpoint in from_list to any endpoint in to_list must be less than delay_value.

 

The tool automatically derives the individual maximum delay targets from clock waveforms and port input or output delays. For more information, refer to the create_clock, set_input_delay, and set_output_delay commands.

 

The maximum delay constraint is a timing exception. This constraint overrides the default single cycle timing relationship for one or more timing paths. This constraint also overrides a multicycle path constraint.

 

 

Examples

The following example sets a maximum delay by constraining all paths from ff1a:CLK or ff1b:CLK to ff2e:D with a delay less than 5 ns:

 

set_max_delay 5 -from {ff1a:CLK ff1b:CLK} -to {ff2e:D}

 

The following example sets a maximum delay by constraining all paths to output ports whose names start by “out” with a delay less than 3.8 ns:

 

set_max_delay 3.8 -to [get_ports out*]