一、Verilog编程学习
1、门电路
1.1、与门
module top_module(
input a,
input b,
output out );
assign out = a&b;
endmodule
1.2、或非门
module top_module(
input a,
input b,
output out );
assign out = ~(a|b);
endmodule
1.3、同或门
module top_module(
input a,
input b,
output out );
assign out = ~(a^b);
endmodule
2、组合电路
2.1、Declaring wires
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n );
wire and_ab;
wire and_cd;
assign and_ab = a&b;
assign and_cd = c&d;
assign out = and_ab|and_cd;
assign out_n = ~out;
endmodule
2.2、7458
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
wire p11, p12, p21, p22;
assign p11 = (p1a&p1b&p1c);
assign p12 = (p1d&p1e&p1f);
assign p21 = (p2a&p2b);
assign p22 = (p2c&p2d);
assign p1y = p11 | p12;
assign p2y = p21 | p22;
endmodule
2.3、7420
module top_module (
input p1a, p1b, p1c, p1d,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = ~(p1a&p1b&p1c&p1d);
assign p2y = ~(p2a&p2b&p2c&p2d);
endmodule
3、时序电路
3.1、d触发器
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q );//
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
always@(posedge clk) begin
q <= d;
end
endmodule
3.2、dff8
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always@(posedge clk) begin
q <= d;
end
endmodule
3.3、dff8r
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always@(posedge clk) begin
q <= (~{8{reset}} & d);
end
endmodule
二、Logisim仿真
1、三八译码器
1.1、电路
1.2、真值表
2、一位全加器
2.1、电路
2.2、封装电路
2.3、真值表
3、四位全加器
3.1、电路
3.2、真值表
3.3、演示
三、Quartus仿真
1、原理图输入一位全加器
1.1、创建工程
1.2、绘制原理图
1.3、编译
1.4、rtl图查看
1.5、波形仿真
2、Verilog语言实现一位全加器
2.1、代码
module FullAdder_gate(
input a, b, cin,
output sum, cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | ((a^b)&cin);
endmodule
2.2、rtl原理图
3、原理图输入四位全加器
3.1、电路
3.2、rtl原理图
4、Verilog编写四位全加器
4.1、代码
module FullAdder_four_gate (
input [3:0] a, b,
output [3:0] sum,
input cin,
output cout
);
wire c1, c2, c3;
FullAdder_one_gate f1(a[0], b[0], cin, sum[0], c1);
FullAdder_one_gate f2(a[1], b[1], c1, sum[1], c2);
FullAdder_one_gate f3(a[2], b[2], c2, sum[2], c3);
FullAdder_one_gate f4(a[3], b[3], c3, sum[3], cout);
endmodule
module FullAdder_one_gate (
input a, b, cin,
output sum, cout
);
assign sum = a^b^cin;
assign cout = (a&b)|((a^b)&cin);
endmodule