module simple_fsm (
input wire sys_clk ,
input wire sys_rst_n ,
input wire pi_money ,
output reg po_cola
);
// define signal
// fsm
reg [02:00] CS ;
reg [02:00] NS ;
localparam IDLE = 3'b001 ,
ONE = 3'b010 ,
TWO = 3'b100 ;
// CS
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
CS <= IDLE ;
end else begin
CS <= NS ;
end
end
// NS
always @(*) begin
case (CS)
IDLE : begin
if(pi_money) begin
NS = ONE ;
end else begin
NS = IDLE ;
end
end
ONE : begin
if(pi_money) begin
NS = TWO ;
end else begin
NS = ONE ;
end
end
TWO : begin
if(pi_money) begin
NS = IDLE ;
end else begin
NS = TWO ;
end
end
default: NS = IDLE ;
endcase
end
// state transition condations are too simple , so ignal
// po_cola
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
po_cola <= 0 ;
end else begin
if(CS == TWO && pi_money) begin
po_cola <= 1 ;
end else begin
po_cola <= 0 ;
end
end
end
endmodule