Xilinx® 7 series FPGAs CLBs专题介绍（二）

目录

背景

CLB布局（CLB Arrangement）

ASMBL Architecture

CLB Slices

CLB/Slice Configurations

Slice Description

Look-Up Table (LUT)

Storage Elements

Control Signals

---

背景

本博文是上篇博文的续集：Xilinx® 7 series FPGAs CLBs专题介绍（一），由于博文太长了阅读起来不太方便，所以这篇博文单独出来。

在数据手册上看到这个简单地总结目录还是不错的，这里贴出来并且按照这个目录来进行分别介绍：

This chapter provides a detailed view of the 7 series FPGAs CLB architecture. These details can be useful for design optimization and verification, but are not necessary for initiating a design. This chapter includes:

• CLB Arrangement

Overview of slice locations and features within the CLB

• Slice Description

Complete details of SLICEM and SLICEL

• Look-Up Table (LUT)

Description of the logical function generators

• Storage Elements

Description and controls for the latches and flip-flops

• Distributed RAM (Available in SLICEM Only)

SLICEM ability to use LUTs as writable memory

• Shift Registers (Available in SLICEM Only)

SLICEM ability to use LUTs as shift registers

• Multiplexers

Dedicated gates for combining LUTs into wide functions

• Carry Logic

Dedicated gates and cascading to implement efficient arithmetic functions.

 

本章提供了7系列FPGA CLB架构的详细视图。 这些细节可用于设计优化和验证，但不是启动设计所必需的。

CLB布局（CLB Arrangement）

主要讲述CLB中的Slice的位置以及特征的概述；

The CLBs are arranged in columns in the 7 series FPGAs. The 7 series is the fourth generation to be based on the unique columnar approach provided by the ASMBL™ architecture.

CLB在7系列FPGA中按列排列。 7系列是第四代基于ASMBL™架构提供的独特柱状方法。

ASMBL Architecture

Xilinx created the Advanced Silicon Modular Block (ASMBL) architecture to enable FPGA platforms with varying feature mixes optimized for different application domains. Through this innovation Xilinx offers a greater selection of devices, enabling customers to select the FPGA with the right mix of features and capabilities for their specific design.
Figure 2-1 provides a high-level description of the different types of column-based resources.

Xilinx创建了高级硅模块（ASMBL）架构，使FPGA平台具有针对不同应用领域优化的各种功能组合。 通过这项创新，赛灵思提供了更多的器件选择，使客户能够根据特定设计选择具有适当特性和功能的FPGA。图2-1提供了不同类型的基于列的资源的高级描述。