通过Clocking Wizard定制和生成一个IP核（MMCM）（Virtex7）（ISE版）

目录

 

定制过程

准备进入定制页面

第一页

Clocking features

第二页

第三页

Selecting Optional Ports

第四页

第五页

第六页

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定制过程

准备进入定制页面

首先通过ISE建立一个工程，然后添加New Source，选择IP核生成选项：

进入IP核选择页面，选择FPGA Features and Design下的Clocking，展开有一个Clocking Wizard：

点击Next，进入总结页面：

第一页

Finish之后，进入IP核定制与生成页面，根据Clocking Wizard正式开始定制你的IP核（没有选择Spread Spectrum）：

第一个页面中有个时钟原语选择的选项（Primitive），这里选择MMCM，意思是定制一个混合模式时钟管理器（MMCM）的IP核，如果选择了PLL，那么定制的IP核就是一个PLL IP核了。

Clocking features

下面再介绍一下上图中的一些Clocking features：

The available clocking features are shown for the selected target device. You can select as many features as desired; however, some features consume additional resources, and some can result in increased power consumption. Additionally, certain combinations of features are not allowed. The GUI will either dim out or hide features which are unavailable.
For example, the Dynamic Reconfiguration Port checkbox is not available for selection in the case of DCM and PLL_BASE as both of these do not support this feature.
Clocking features include:

• Frequency synthesis. This feature allows output clocks to have different frequencies than the active input clock.

• Spread Spectrum (SS). This feature provides modulated output clocks which reduces the spectral density of the electromagnetic interference (EMI) generated by electronic devices. This feature is available only for MMCME2 primitive.

• Phase alignment. This feature allows the output clock to be phase locked to a reference, such as the input clock pin for a device. 

• Minimize power. This features minimizes the amount of power needed for the primitive at the possible expense of frequency, phase offset, or duty cycle accuracy.

• Dynamic phase shift. This feature allows you to change the phase relationship on the output clocks.

• Dynamic reconfiguration. This feature allows you to change the programming of the primitive after device configuration. When this option is chosen, the clocking wizard uses only integer values for M, D and CLKOUT[0:6]_DIVIDE.

• Balanced. Selecting Balanced results in the software choosing the correct BANDWIDTH for jitter optimization.

• Minimize output jitter. This feature minimizes the jitter on the output clocks, but at the expense of power and possibly output clock phase error. This feature is not available with ‘Maximize input jitter filtering’.

• Maximize input jitter filtering. This feature allows for larger input jitter on the input clocks, but can negatively impact the jitter on the output clocks. This f