第一种,正儿八经:
带异步复位,同步使能的D触发器:
module dff_reset_en_1seg(
input clk,
input reset,
input en,
input d,
output reg q
);
always @(posedge clk, posedge reset)
begin
if(reset)
q <= 1'b0;
else if(en)
q <= d;
end
endmodule
行为测试:
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2019/01/03 10:39:16
// Design Name:
// Module Name: dff_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module dff_tb;
reg reset;
reg en;
reg CLK;
reg d;
wire q;
// Note: CLK must be